Tunnel field-effect transistor
A tunnel field-effect transistor and method fabricating the same are provided. The tunnel field-effect transistor includes a drain region, a source region with opposite conductive type to the drain region, a channel region disposed between the drain region and the source region, a metal gate layer disposed around the channel region, and a high-k dielectric layer disposed between the metal gate layer and the channel region.
1. A tunnel field-effect transistor comprising:
a substrate;
a semiconductor column protruding from the substrate;
a drain region disposed as a first portion of the semiconductor column;
a source region disposed as a second portion of the semiconductor column, wherein the drain and source regions are of opposite conductive types;
a channel region disposed as a third portion of the semiconductor column and between the drain region and the source region;
a metal gate layer surrounding the channel region;
a high-k dielectric layer disposed between the metal gate layer and the channel region;
a sidewall spacer disposed around the source region; and
a gate contact connected to the metal gate layer, wherein the gate contact is in contact with the sidewall spacer and is self-aligned by the sidewall spacer.
2. The tunnel field-effect transistor of claim 1 , wherein at least one of the source region, the drain region, and the channel region has a graded doping concentration.
3. The tunnel field-effect transistor of claim 1 , further comprising:
an insulation layer disposed at least around the sidewall spacer, wherein the insulation layer and the sidewall spacer are made of different materials.
4. The tunnel field-effect transistor of claim 1 , wherein a width of a first portion of the gate contact that is above the sidewall spacer is larger than a width of a second portion of the gate contact that is under the sidewall spacer.
5. A tunnel field-effect transistor component comprising:
a substrate having a first-type well, a second-type well, and a shallow trench isolation feature separating the first-type well and the second-type well;
a first-type tunnel field-effect transistor disposed on the second-type well, the first-type tunnel field-effect transistor comprising:
a first-type drain region;
a second-type source region;
a first-type channel region disposed between the first-type drain region and the second-type source region;
a first metal gate layer encircling the first-type channel region; and
a first high-k dielectric layer disposed between the first metal gate layer and the first-type channel region;
a first work function metal layer disposed between the first high-k dielectric layer and the first metal gate layer; and
a second-type tunnel field-effect transistor disposed on the first-type well, the second-type tunnel field-effect transistor comprising:
a second-type drain region;
a first-type source region;
a second-type channel region disposed between the second-type drain region and the first-type source region;
a second metal gate layer encircling the second-type channel region; and
a second high-k dielectric layer disposed between the second metal gate layer and the second-type channel region.
6. The tunnel field-effect transistor component of claim 5 , wherein the first-type drain region, the second-type source region, and the first-type channel region are substantially vertically stacked.
7. The tunnel field-effect transistor component of claim 5 , wherein the second-type drain region, the first-type source region, and the second-type channel region are substantially vertically stacked.
8. The tunnel field-effect transistor component of claim 5 , wherein a doping concentration of the second-type source region is larger than a doping concentration of the first-type drain region.
9. The tunnel field-effect transistor component of claim 5 , wherein at least one of the first-type source region, the first-type drain region, the first-type channel region, the second-type source region, the second-type drain region, and the second-type channel region has a graded doping concentration.
10. The tunnel field-effect transistor component of claim 5 , further comprising:
a silicide region formed on the first-type source region and the second-type source region; and
a plurality of sidewall spacers respectively disposed around the first-type and second-type source regions, and disposed between the silicide region and the first and second metal gate layers.
11. The tunnel field-effect transistor of claim 1 , further comprising a work function metal layer disposed between the high-k dielectric layer and the metal gate layer.
12. The tunnel field-effect transistor of claim 1 , further comprising an interfacial layer disposed between the high-k dielectric layer and the substrate.
13. The tunnel field-effect transistor of claim 1 , wherein the drain region is disposed between the substrate and the channel region.
14. The tunnel field-effect transistor of claim 13 , further comprising a silicide region formed on the source region.
15. The tunnel field-effect transistor component of claim 5 , further comprising:
a second work function metal layer disposed between the second high-k dielectric layer and the second metal gate layer and having the same conductive type as the first work function metal layer; and
a third work function metal layer disposed between the second high-k dielectric layer and the second metal gate layer and having a conductive type opposite to the conductive type of the first work function metal layer.
16. The tunnel field-effect transistor component of claim 5 , wherein the first-type drain region is disposed between the second-type well and the first-type channel region, and the second-type drain region is disposed between the first-type well and the second-type channel region.
17. The tunnel field-effect transistor of claim 1 , further comprising an electrode disposed on the gate contact.
18. The tunnel field-effect transistor of claim 17 , wherein the electrode is in direct contact with the gate contact.
19. A tunnel field-effect transistor comprising:
a substrate;
a drain region on the substrate;
a source region above the drain region, wherein the drain and source regions are of opposite conductive types;
a channel region between the drain region and the source region;
an insulation layer surrounding the drain region;
an etch stop layer between the drain region and the insulation layer and surrounding the drain region; and
a gate dielectric layer surrounding the channel region and above the etch stop layer.
20. The tunnel field-effect transistor of claim 19 , wherein the gate dielectric layer is in contact with the channel region.