Dual channel memory
View Patent ↗Technologies are generally described related to a dual channel memory device, system and method of manufacture. Various described devices include utilization of both a front channel and a back channel through a substrate formed underneath a dual gate structure of a semiconductor device. Using two pairs of contacts on opposing sides of the gate structure, where the contact pairs are formed on differently doped layers of the semiconductor device, multiple bits may be stored in the semiconductor device acting as a single memory cell. Memorization may be realized by storing different amount or types of charges on the floating gate, where the charges may impact a conduction status of the channels of the device. By detecting the conduction status of the channels, such as open circuit, close circuit, or high resistance, low resistance, data stored on the device (“0” or “1”) may be detected.
1. A semiconductor device comprising:
a first substrate;
an insulator layer positioned over the first substrate;
a second substrate positioned over the insulator layer;
a gate structure comprising:
a tunnel oxide layer positioned over a protrusion of the second substrate, wherein the protrusion of the second substrate includes a width that is about equal to a width of the tunnel oxide layer;
a floating gate layer positioned over the tunnel oxide layer;
a control oxide layer positioned over the floating gate layer;
a control gate layer positioned over the control oxide layer; and
a third substrate positioned over a recessed portion of the second substrate,
wherein the protrusion of the second substrate is located substantially central to the recessed portion of the second substrate, and
wherein the recessed portion of the second substrate includes dopants of a first type and the third substrate includes dopants of a second type.
2. The semiconductor device of claim 1 , further comprising:
a first pair of contacts configured to contact the third substrate on opposite sides of the gate structure; and
a second pair of contacts configured to contact the recessed portion of the second substrate on opposite sides of the gate structure.
3. The semiconductor device of claim 2 , wherein the third substrate is positioned around the protrusion of the second substrate.
4. The semiconductor device of claim 2 , wherein the second pair of contacts are positioned over the recessed portion of the second substrate between an edge of the semiconductor device and the third substrate.
5. The semiconductor device of claim 1 , further comprising a spacer formed along, vertical surfaces of the gate structure, wherein the gate structure and the spacer are positioned to cover a lateral cross-section of the protrusion of the second substrate.
6. The semiconductor device of claim 1 , wherein the dopants of the first type are p dopants and wherein the dopants of the second type are n dopants.
7. The semiconductor device of claim 1 , wherein the semiconductor device is a dual channel memory device.
8. The semiconductor device of claim 1 , wherein the first substrate includes one of silicon, germanium, a group II semiconductor material, a group III semiconductor material, a group IV semiconductor material, a group V semiconductor material, and a group VI semiconductor material.
9. The semiconductor device of claim 1 , wherein the second substrate includes one of silicon, germanium, a group II semiconductor material, a group III semiconductor material, a group IV semiconductor material, a group V semiconductor material, and a group VI semiconductor material.
10. The semiconductor device of claim 1 , wherein the protrusion of the second substrate includes the width that is about larger than the width of the tunnel oxide layer.
11. The semiconductor device of claim 1 , wherein fast annealing is employed to reduce dopant diffusion in the dopants of the second type.