IP Library Patent Application 14461090
Patent Application
App. No. 14/461,090

Combined Transmission Precompensation and Receiver Nonlinearity Mitigation

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Patent No.
US None
App. No.
14/461,090
Abstract

Circuitry of a transmitter may comprise a predistortion circuit cascaded with a nonlinear circuit. The nonlinear circuit may be characterized by a first response corresponding to a first error vector magnitude. A response of the predistortion circuit may be configured based on the first response of the nonlinear circuit such that a composite response of the predistortion circuit cascaded with the nonlinear circuit differs from the first response and is characterized by a second error vector magnitude that is greater or equal than the first error vector magnitude. The response of the predistortion circuit may be configured based on feedback of an output of the nonlinear circuit. The response of the predistortion circuit may be configured based on parameters received from a receiver partner of the transmitter during connection setup, in preambles, in message headers, and/or in dedicated messages.

Claims (39)

1 . A system comprising:

circuitry of a transmitter comprising a predistortion circuit cascaded with a nonlinear circuit, wherein:

said nonlinear circuit is characterized by a first response corresponding to a first error vector magnitude; and

a response of said predistortion circuit is configured based on said first response of said nonlinear circuit such that a composite response of said predistortion circuit cascaded with said nonlinear circuit differs from said first response and is characterized by a second error vector magnitude that is greater or equal than said first error vector magnitude.

2 . The system of claim 1 , wherein said response of said predistortion circuit is configured based on feedback of an output of said nonlinear circuit.

3 . The system of claim 1 , wherein said response of said predistortion circuit is configured based on parameters received from a receiver partner of said transmitter during connection setup, in preambles, in message headers, and/or in dedicated messages.

4 . The system of claim 3 , wherein said parameters indicate a figure of merit.

5 . The system of claim 1 , wherein said nonlinear circuit comprises a power amplifier.

6 . The system of claim 5 , wherein said response of said predistortion circuit is configured based on a power backoff setting of said power amplifier.

7 . The system of claim 1 , wherein:

said response of said predistortion circuit is characterized by one or more predistortion parameters; and

said circuitry of said transmitter is operable to transmit said one or more predistortion parameters during connection setup, in preambles, in message headers, and/or in dedicated messages.

8 . The system of claim 1 , wherein said response of said predistortion circuit is configured to compensate for a first portion of a nonlinearity of said response of said nonlinear circuit but not compensate for a second portion of said nonlinearity of said response of said nonlinear circuit.

9 . The system of claim 8 , wherein:

said nonlinearity of said nonlinear circuit can be expressed as a sum of a plurality of terms; and

said first portion of said nonlinearity of said response of nonlinear circuit corresponds to a subset of higher-order terms of said plurality of terms.

10 . The system of claim 8 , wherein:

said nonlinearity of said nonlinear circuit can be expressed as a sum of a plurality of terms; and

said first portion of said nonlinearity of said response of nonlinear circuit corresponds to a subset of said plurality of terms consisting of non-causal terms of said plurality of terms.

11 . A system comprising:

circuitry of a transmitter comprising a predistortion circuit cascaded with a nonlinear circuit, wherein:

a composite response of said predistortion circuit cascaded with said nonlinear circuit is characterized by a first error vector magnitude when said predistortion circuit is enabled;

said composite response of said predistortion circuit cascaded with said nonlinear circuit is characterized by a second error vector magnitude when said predistortion circuit is disabled; and

said first error vector magnitude is greater than said second error vector magnitude.

12 . The system of claim 11 , wherein said response of said predistortion circuit is configured based on feedback of an output of said nonlinear circuit.

13 . The system of claim 11 , wherein said response of said predistortion circuit is configured based on parameters received from a receiver partner of said transmitter during connection setup, in preambles, in message headers, and/or in dedicated messages.

14 . The system of claim 13 , wherein said parameters indicate a figure of merit.

15 . The system of claim 13 , wherein said nonlinear circuit comprises a power amplifier.

16 . The system of claim 15 , wherein said predistortion circuit is configured based on a power backoff setting of said power amplifier.

17 . The system of claim 11 , wherein:

said predistortion circuit is configured via one or more predistortion parameters; and

said circuitry of said transmitter is operable to transmit said one or more predistortion parameters during connection setup, in preambles, in message headers, and/or in dedicated messages.

18 . The system of claim 11 , wherein said predistortion circuit is configured to compensate for a first portion of a nonlinearity of a response of said nonlinear circuit but not compensate for a second portion of said nonlinearity of said response of said nonlinear circuit.

19 . The system of claim 18 , wherein:

said nonlinearity of said nonlinear circuit can be expressed as a sum of a plurality of terms; and

said first portion of said nonlinearity of said response of nonlinear circuit corresponds to a subset of higher-order terms of a said plurality of terms.

20 . The system of claim 18 , wherein:

said nonlinearity of said nonlinear circuit can be expressed as a sum of a plurality of terms; and

said first portion of said nonlinearity of said response of nonlinear circuit corresponds to a subset of said plurality of terms consisting of non-causal terms of said plurality of terms.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: MAGNACOM LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041604/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 22, 2014
From: ELIAZ, AMIR; REUVEN, ILAN; INTRATER, AMOS; STOPLER, DANIEL; OREN, ROY; BENJO, SHIMON; PITARASHO, GAL
To: MAGNACOM LTD.
Reel/Frame 034006/0171 →