CPU utilization metering on systems that include multiple hardware threads per core

1. A method comprising:

implementing a performance counter associated with one or more hardware threads;

counting events associated with the one or more hardware threads to determine an event count;

deriving an initial measure of usage of a processor core associated with the one or more hardware threads based at least in part on the event count over an interval of time, wherein the initial measure of usage is based at least in part on a percentage of time a system, a core, or a hardware thread is idle, or a percentage of time the system, the core, or the hardware is active;

correcting one or more inaccuracies in the initial measure of usage, wherein the correcting of the one or more inaccuracies includes applying a corrective function to modify the initial measure of usage and determine a modified measure of usage over the interval of time, wherein the modified measure of usage has a value that is different from and not equivalent to the initial measure of usage; and

outputting an indication of a processor usage, the indication being based at least in part on the modified measure of usage.

2. A method as recited in claim 1 , wherein the events are associated with more than one hardware thread.

3. A method as recited in claim 1 , wherein the events are associated with a processor core on a system.

4. A method as recited in claim 1 , wherein the events are associated with the system.

5. A method as recited in claim 1 , wherein counting includes counting instructions executed.

6. A method as recited in claim 1 , wherein counting includes counting cycles.

7. A method as recited in claim 1 , wherein counting includes counting an event associated with utilization.

8. A method as recited in claim 1 , wherein counting includes counting idle cycles.

9. A method as recited in claim 1 , wherein counting includes counting utilized cycles.

10. A method as recited in claim 1 , wherein counting includes counting utilized memory and/or prefetch bandwidth.

11. A method as recited in claim 1 , wherein counting includes counting cache misses.

12. A method as recited in claim 1 , wherein deriving includes calculating a loaded core CPI.

13. A method as recited in claim 1 , wherein deriving includes calculating an average core CPI.

14. A method as recited in claim 1 , wherein deriving includes calculating a core instructions per second potential (CIPSP).

15. A method as recited in claim 1 , wherein deriving includes instrumenting a “single threaded” CPI associated with a software thread.

16. A method as recited in claim 1 , wherein deriving includes modeling an amount of “empty cycles” in a processor core using “single threaded” CPI information.

17. A method as recited in claim 1 , wherein the corrective function is determined based at least in part on measuring or probing a system that includes the processor core.

18. A system including:

one or more processors that:

implement a performance counter associated with one or more hardware threads;

count events associated with the one or more hardware threads to determine an event count;

derive an initial measure of usage of a processor core associated with the one or more hardware threads based at least in part on the event count over an interval of time, wherein the initial measure of usage is based at least in part on a percentage of time a system, a core, or a hardware thread is idle, or a percentage of time the system, the core, or the hardware is active;

correct one or more inaccuracies in the initial measure of usage, wherein to correct of the one or more inaccuracies includes to apply a corrective function to modify the initial measure of usage and determine a modified measure of usage over the interval of time, wherein the modified measure of usage has a value that is different from and not equivalent to the initial measure of usage; and

output an indication of a processor usage, the indication being based at least in part on the modified measure of usage; and

one or more memories coupled with the one or more processors, wherein the one or more memories provide the one or more processors with instructions.

19. A computer program product for indicating processor usage in a system, the computer program product being embodied in a tangible non-transitory computer readable medium and comprising computer instructions for:

implementing a performance counter associated with one or more hardware threads;

counting events associated with the one or more hardware threads to determine an event count;

deriving an initial measure of usage of a processor core associated with the one or more hardware threads based at least in part on the event count over an interval of time, wherein the initial measure of usage is based at least in part on a percentage of time a system, a core, or a hardware thread is idle, or a percentage of time the system, the core, or the hardware is active;

correcting one or more inaccuracies in the initial of measure usage, wherein the correcting of the one or more inaccuracies includes applying a corrective function to modify the initial measure of usage and determine a modified measure of usage over the interval of time, wherein the modified measure of usage has a value that is different from and not equivalent to the initial measure of usage; and

outputting an indication of a processor usage, the indication being based at least in part on the modified measure of usage.

20. The method of claim 1 , wherein the corrective function is heuristically determined.

21. The method of claim 1 , wherein the corrective function is determined according to a measured workload of the one or more hardware threads.

22. The method of claim 1 , wherein the corrective function is determined using profiling information associated with the software threads or processes in the processor core.

23. The method of claim 1 , wherein the initial measure of usage is measured according to a first unit, and the modified initial measure of usage is represented in the first unit.