Low-noise high efficiency bias generation circuits and method

1. An apparatus for generating a substantially steady state positive voltage signal (PVS) and a substantially steady state negative voltage signal (NVS) to a switching module (SM), the SM being adapted to modulate a radio frequency (RF) signal, the PVS and the NVS remaining substantially stable during a switching event of the SM, the apparatus including:

a bias signal generation module (BSGM) for generating a substantially steady state reference voltage signal (RVS), the RVS having a voltage level nominally less than the PVS;

a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to nominally generate a portion of the PVS based on the RVS, the PSGM further including:

a positive voltage charge pump signal generation module (PVCPGM), the PVCPGM generating a voltage signal (VPOS) based on a fixed internal positive voltage (VDD_INT) in correspondence of PVS, VPOS having a voltage level equal to or larger than PVS; and

a PSGM differential module coupled to the PVCPGM and biased with a PSGM differential bias current driven by the RVS, the PSGM differential module controlling the PVS; and

a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to nominally generate a portion of the NVS based on the RVS, the NGSM further including:

a negative voltage charge pump signal generation module (NVCPGM), the NVCPGM generating a voltage signal (VNEG) based on VDD_INT in correspondence of NVS, VNEG having a voltage level in magnitude equal to or larger than NVS; and

a NSGM differential module coupled to the NVCPGM and biased with a NSGM differential bias current driven by the RVS, the NSGM differential module controlling the NVS.

2. The apparatus of claim 1 , wherein the ratio of the VPOS voltage magnitude to the VDD_INT voltage magnitude is larger than one.

3. The apparatus of claim 2 , wherein the ratio of the VPOS voltage magnitude to the VDD_INT voltage magnitude is two.

4. The apparatus of claim 3 , wherein the fixed VDD_INT voltage is 2.3 volts.

5. The apparatus of claim 2 , the PSGM generating a positive capacitor control signal (PCCS) based at least partially on the RVS and employing the first capacitor to nominally generate a portion of the PVS at least partially based on the PCCS, and/or the NSGM generating a negative capacitor control signal (NCCS) based at least partially on the RVS and employing the second capacitor to nominally generate a portion of the NVS at least partially based on the NCCS.

6. The apparatus of claim 5 , wherein the ratio of the PVS voltage magnitude to the RVS voltage magnitude is about 1.5 to 4 and optionally wherein the ratio of the NVS voltage magnitude to the RVS voltage magnitude is about 1.5 to 4.

7. The apparatus of claim 2 , the BSGM employing a first FET element and a second FET element formed on a common silicon on insulator (SOI) wafer in part to generate the RVS where the RVS is temperature independent.

8. The apparatus of claim 2 , the BSGM further generating a first field effect transistor (FET) bias signal and a second FET bias signal, the PSGM at least employing the first FET bias signal, and the NSGM at least employing the second FET bias signal.

9. The apparatus of claim 8 , wherein the PSGM employs the first FET bias signal at least partially to generate a current drain and optionally wherein the NSGM employs the second FET bias signal at least partially to generate a current source.

10. The apparatus of claim 9 , wherein the PSGM differential module employs the current drain and determines a difference between the PVS signal voltage level and the RVS voltage level and optionally, comprises a low drop out (LDO) regulator, the difference and the LDO controlling the PVS, and optionally wherein the NSGM differential module employs the current source and determines the difference between the NVS signal voltage level and the RVS voltage level.

11. The apparatus of claim 9 , wherein the BSGM generates an internal, substantially stable, voltage signal (IVS) based on at least partially on the first FET bias signal and the RVS.

12. The apparatus of claim 11 , wherein the PSGM generates the PVS in part with the IVS and optionally wherein the NSGM generates the NVS in part with the IVS.

13. The apparatus of claim 11 , wherein the PSGM employs the first capacitor to nominally generate about half of the voltage level of the PVS and optionally wherein the NSGM employs the second capacitor to nominally generate about half of the magnitude of the voltage level of the NVS.

14. The apparatus of claim 1 , wherein the BSGM generates the VDD_INT, VDD_INT having a voltage level equal to or smaller than RVS.