Semiconductor Device and Manufacturing Method Thereof
Provided are a semiconductor device in which the occurrence of a short circuit between a gate electrode and either of the source/drain regions of a transistor can be suppressed and a manufacturing method thereof. In the semiconductor device, a first insulating layer formed over the gate electrode and containing a silicon nitride has an upper surface having a depressed portion which is formed in a region over a second electrode layer of the gate electrode containing a silicide.
1 . A semiconductor device, comprising:
a semiconductor substrate having a main surface;
a gate electrode formed over the main surface of the semiconductor substrate;
a side-wall oxide film formed over a side wall of the gate electrode; and
a first insulating layer formed over the gate electrode and containing a silicon nitride,
wherein the gate electrode includes a first electrode layer containing silicon, and a second electrode layer formed over the first electrode layer and containing a silicide, and
wherein the first insulating layer has an upper surface opposite to the main surface and having a depressed portion formed in a region over the second electrode layer.
2 . A semiconductor device according to claim 1 , further comprising:
a pair of source/drain regions formed in the main surface of the semiconductor substrate with a channel formation region located under the gate electrode being interposed therebetween,
wherein the depressed portion is formed so as to extend in parallel with each of the pair of source/drain regions along a gate width direction of the gate electrode.
3 . A semiconductor device according to claim 2 ,
wherein the depressed portion has a length larger than a length of each of the pair of source/drain regions in plan view.
4 . A semiconductor device according to claim 1 , further comprising:
a second insulating layer formed between the gate electrode and the first insulating layer and containing a silicon dioxide,
wherein the depressed portion is formed so as to extend through the first insulating layer and expose a part of the second insulating layer from the first insulating layer.
5 . A semiconductor device according to claim 4 ,
wherein the second insulating layer has a through hole communicating with the depressed portion, and
wherein the depressed portion and the through hole are formed so as to expose a part of the second electrode layer from the first and second insulating layers.
6 . A semiconductor device according to claim 1 ,
wherein the depressed portion has a linear portion formed in a linear shape in plan view.
7 . A semiconductor device according to claim 6 ,
wherein the depressed portion further has first and second tip portions extending respectively from one end and the other end of the linear portion in a gate length direction of the gate electrode in plan view.
8 . A semiconductor device according to claim 7 ,
wherein the depressed portion is formed in an annular shape in plan view.
9 . A method of manufacturing a semiconductor device, comprising the steps of:
providing a semiconductor substrate having a main surface;
forming, over the main surface, a gate electrode including a first electrode layer containing silicon, and a second electrode layer formed over the first electrode layer and containing a silicide;
forming, over the gate electrode, a first insulating layer containing a silicon nitride and having an upper surface opposite to the main surface and formed with a depressed portion; and
forming, over a side surface of the gate electrode, a side-wall oxide film after the first insulating layer having the depressed portion is formed.