High-voltage level conversion circuit

1. A high-voltage level conversion circuit comprising:

a first NMOS transistor, the gate of the first NMOS transistor connected to an input terminal for receiving an input signal, the source of the first NMOS transistor connected to a first voltage level, wherein the input signal comprises the first voltage level and a second voltage level;

a first PMOS transistor, the gate of the first PMOS transistor connected to the input terminal for receiving the input signal, the source of the first PMOS transistor connected to the second voltage level;

a second NMOS transistor, the drain of the second NMOS transistor connected to the drain of the first PMOS transistor, the gate and the drain of the second NMOS transistor connected together, thus the voltage across the second NMOS transistor being at least a threshold voltage when the second NMOS transistor is conducted;

a second PMOS transistor, the drain of the second PMOS transistor connected to the drain of the first NMOS transistor, the gate and the drain of the second PMOS transistor connected together, thus the voltage across the second PMOS transistor being at least a threshold voltage when the second PMOS transistor is conducted;

a third PMOS transistor, the drain of the third PMOS transistor connected to the source of the second PMOS transistor, the source of the third PMOS transistor connected to a third voltage level;

a third NMOS transistor, the drain of the third NMOS transistor connected the source of the second NMOS transistor, the source of the third NMOS transistor connected to a fourth voltage level;

a fourth PMOS transistor, the gate of the fourth PMOS transistor connected to the drain of the first NMOS transistor, the source of the fourth PMOS transistor receiving the third voltage level, the drain of the fourth PMOS transistor connected to the gate of the third NMOS transistor; and

a fourth NMOS transistor, the gate of the fourth NMOS transistor connected to the drain of the first PMOS transistor, the source of the fourth NMOS transistor receiving the fourth voltage level, the drain of the fourth NMOS transistor connected to the gate of the third PMOS transistor;

wherein the drain of the fourth PMOS transistor and the drain of the fourth NMOS transistor are for generating a high-voltage level conversion signal.

2. The high-voltage level conversion circuit according to claim 1 , wherein the first voltage level is lower than the second voltage level, the second voltage level is lower than the third voltage level, the fourth voltage level is lower the first voltage level.

3. The high-voltage level conversion circuit according to claim 2 , wherein the source of the fourth PMOS transistor is connected to the third voltage level, the source of the fourth NMOS transistor is connected to the fourth voltage level, the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor for being an output terminal, the output terminal provides the high-voltage level conversion signal.

4. The high-voltage level conversion circuit according to claim 2 , wherein when the input signal changes from the first voltage level to the second voltage level the first NMOS transistor is turned on and the first PMOS transistor is turned off, then the voltage of the drain of the first NMOS transistor is gradually pulled down to the first voltage level, and the fourth PMOS transistor is turned on to pull up the voltage of the output terminal so as to cause the third NMOS transistor to be turned on, thus the voltage of the drain of the first PMOS transistor is pulled down to the fourth voltage level added with the threshold voltage in order to turn off the fourth NMOS transistor for pulling up the voltage of the output terminal to the third voltage level.

5. The high-voltage level conversion circuit according to claim 4 , wherein when the voltage of the output terminal is pulled up to the third voltage level, the third PMOS transistor is turned off.

6. The high-voltage level conversion circuit according to claim 2 , wherein when the input signal changes from the second voltage level to the first voltage level, the first NMOS transistor is turned off and the first PMOS transistor is turned on, then the voltage of the drain of the third NMOS transistor is pulled up to the second voltage level, and the fourth NMOS transistor is turned on to pull down the voltage of the output terminal so as to cause the third PMOS transistor to be turned on, thus the voltage of the drain of the first NMOS transistor is pulled up to the third voltage level minus the threshold voltage in order to turn off the fourth PMOS transistor for pulling down the voltage of the output terminal to the fourth voltage level.

7. The high-voltage level conversion circuit according to claim 6 , wherein when the voltage of the output terminal is pulled down to the fourth voltage level, the third NMOS transistor is turned off.

8. The high-voltage level conversion circuit according to claim 2 , wherein the drain of the fourth NMOS transistor is connected to the drain of the fourth PMOS transistor for generating the high-voltage level conversion signal, the high-voltage level conversion circuit further comprises:

a fifth PMOS transistor, the gate of the fifth PMOS transistor connected to the drain of the fourth PMOS transistor, the drain of the fifth PMOS transistor connected to the source of the fourth PMOS transistor, the source of the fifth PMOS transistor connected to the third voltage level, wherein the source of the fourth PMOS transistor receives the third voltage level via the fifth PMOS transistor; and

a fifth NMOS transistor, the gate of the fifth NMOS transistor connected to the drain of the fourth NMOS transistor, the drain of the fifth NMOS transistor connected to the source of the fourth NMOS transistor, the source of the fifth NMOS transistor connected to the fourth voltage level, wherein the source of the fourth NMOS transistor receives the fourth voltage level via the fifth NMOS transistor.

9. The high-voltage level conversion circuit according to claim 8 , further comprising:

a sixth PMOS transistor, the source of the sixth PMOS transistor connected to the third voltage level, the gate of the sixth PMOS transistor connected to the drain of the fourth PMOS transistor; and

a sixth NMOS transistor, the source of the sixth NMOS transistor connected to the fourth voltage level, the gate of the sixth NMOS transistor connected to the drain of the fourth NMOS transistor, the drain of the sixth NMOS transistor connected to the drain of the sixth PMOS transistor for being an output terminal.

10. The high-voltage level conversion circuit according to claim 2 , wherein the source of the fourth PMOS transistor is connected to the third voltage level, the source of the fourth NMOS transistor is connected to the fourth voltage level, the high-voltage level conversion circuit further comprises:

a fifth PMOS transistor, the gate and the drain of the fifth PMOS transistor connected to the drain of the fourth NMOS transistor, the source of the fifth PMOS transistor connected to the drain of the fourth PMOS transistor;

a fifth NMOS transistor, the gate and the drain of the fifth NMOS transistor connected to the drain of the fourth PMOS transistor, the source of the fifth NMOS transistor connected to the drain of the fourth NMOS transistor;

a sixth PMOS transistor, the source of the sixth PMOS transistor connected to the third voltage level, the gate of the sixth PMOS transistor connected to the drain of the fourth PMOS transistor; and

a sixth NMOS transistor, the source of the sixth NMOS transistor connected to the fourth voltage level, the gate of the sixth NMOS transistor connected to the drain of the fourth NMOS transistor, the drain of the sixth NMOS transistor connected to the drain of the sixth PMOS transistor for being an output terminal.