IP Library › Granted Patent US 9,165,845
Granted Patent B2
US 9,165,845 · App. 14/465,975 · Granted Oct 20, 2015

Semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,165,845
App. No.
14/465,975
Granted
Oct 20, 2015
Kind
B2
Abstract

Provided is a semiconductor device having a pad on a semiconductor chip, a first passivation film formed over the semiconductor chip and having an opening portion on the pad of a probe region and a coupling region, a second passivation film formed over the pad and the first passivation film and having an opening portion on the pad of the coupling region, and a rewiring layer formed over the coupling region and the second passivation film and electrically coupled to the pad. The pad of the probe region placed on the periphery side of the semiconductor chip relative to the coupling region has a probe mark and the rewiring layer extends from the coupling region to the center side of the semiconductor chip. The present invention provides a technology capable of achieving size reduction, particularly pitch narrowing, of a semiconductor device.

Claims (28)

1. A semiconductor device comprising:

a semiconductor chip including a main surface, and having a pad formed over the main surface, a probe mark being formed in a first area of a surface of the pad;

a first insulating film formed over the main surface of the semiconductor chip and having an opening portion, a second area of the surface of the pad being exposed from the opening portion of the first insulating film; and

a wiring line formed over the first insulating film,

wherein, in a plan view, the second area is disposed closer than the first area to a central portion of the main surface of the semiconductor chip,

wherein the wiring line is connected with the pad at the second area of the surface of the pad, but not at the first area of the surface of the pad, and

wherein, in the plan view, the wiring line is led toward the central portion of the main surface from the second area.

2. The semiconductor device according to claim 1 ,

wherein the first area of the surface of the pad is covered with the first insulating film.

3. The semiconductor device according to claim 1 ,

wherein a second insulating film is formed over the main surface;

wherein the second insulating film has an opening portion;

wherein the surface of the pad is exposed from the opening portion of the second insulating film; and

wherein the first insulating film is formed over the second insulating film.

4. The semiconductor device according to claim 1 ,

wherein a third insulating film is formed over the first insulating film;

wherein the third insulating film has an opening portion;

wherein a part of the wiring line is exposed from the opening portion of the third insulating film.

5. The semiconductor device according to claim 4 ,

wherein a bump electrode is formed inside of the opening portion of the third insulating film.

6. The semiconductor device according to claim 1 ,

wherein a bump electrode is connected with a part of the wiring line.

7. The semiconductor device according to claim 1 ,

wherein the wiring line is connected with the pad via a seed layer.

8. The semiconductor device according to claim 7 ,

wherein the seed layer is formed over the first insulating film;

wherein the seed layer is connected with the pad at the second area of the surface of the pad, but not at the first area of the surface the pad; and

wherein the wiring line is formed over the first insulating film via the seed layer.

Assignments (1)
CHANGE OF ADDRESS Recorded Nov 29, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 044928/0001 →