Semiconductor apparatus
View Patent ↗A semiconductor apparatus includes: a variable delay unit configured to delay a reference clock signal in response to a delay code and generate a data latch clock signal; a delay amount control unit configured to convert a phase of external data and a phase of the data latch clock signal into first and second codes, respectively, and generate the delay code through a calculation of the first and second codes; and a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.
1. A semiconductor apparatus comprising:
a data latch clock generator configured to generate a data latch clock signal by delaying a reference clock signal in response to external data and the data latch clock signal;
a data receiver configured to latch the external data as internal data in synchronization with the data latch clock signal.
2. The semiconductor apparatus according to claim 1 ,
wherein the data latch clock generator controls a delay amount of the reference clock signal such that the external data and the data latch clock signal have a preset phase difference.
3. The semiconductor apparatus according to claim 2 ,
wherein the preset phase difference is substantially 90 degrees.
4. The semiconductor apparatus according to claim 2 ,
wherein the data latch clock generator generates a delay code according to a difference between a phase of the data latch clock signal and a phase of the external data, and generates the data latch clock signal by delaying the reference clock signal in response to the delay code.
5. The semiconductor apparatus according to claim 4 ,
wherein the data latch clock generator comprises:
a first converter configured to generate the phase of the external data as a first code;
a second converter configured to generate the phase of the data latch clock signal as a second code;
a calculator configured to calculate a difference between the first and second codes and generate the delay code; and
a variable delay unit configured to delay the reference clock signal in response to the delay code and generate the data latch clock signal.
6. The semiconductor apparatus according to claim 5 ,
wherein the first converter is configured to generate a rising time point of the external data before a rising time point of the data latch clock signal as the first code, based on the rising time point of the data latch clock signal.
7. The semiconductor apparatus according to claim 5 ,
wherein the second converter is configured to generate a rising time point of the data latch clock signal before a rising time point of inverted external data as the second code, based on the rising time point of the inverted external data.