Methods and apparatus for an improved analog to digital converter
View Patent ↗An improved analog to digital converter comprises at least one delta sigma analog to digital converter stage and a succession of pipelined analog to digital converter stages. The pipelined analog to digital converter stages may have a sampling rate determined separately from that of the at least one delta-sigma analog to digital converter stage. The sampling rate of the at least one delta sigma analog to digital converter stage may be an oversampling rate. The sampling rate of the at least one delta-sigma analog to digital converter stages and the pipeline stages may be adjusted by adjusting their sampling frequency and the number of effective pipeline stages may be adjusted—for example, by adjusting a sampling frequency input at each stage. The effective number of pipeline stages may be adjusted, for example, based on the precision needed to process the current signal.
1. An analog to digital converter comprising:
at least one delta-sigma analog to digital converter stage;
a succession of pipelined analog to digital converter stages;
wherein the pipelined analog to digital converter stages exhibit a sampling rate determined separately from that of the at least one delta-sigma analog to digital converter stage.
2. The analog to digital converter of claim 1 , wherein the sampling rates of the at least one delta-sigma analog to digital converter stage and the pipelined analog to digital converter stages are adjustable.
3. The analog to digital converter of claim 2 , wherein the sampling rate of each stage is adjusted by adjusting a sampling frequency of the stage.
4. The analog to digital converter of claim 1 , wherein the number of pipelined analog to digital converter stages is programmable.
5. The analog to digital converter of claim 4 , wherein the number of pipelined analog to digital converter stages is programmable based on the precision required to process the current signal.
6. The analog to digital converter of claim 1 , wherein the pipelined analog to digital converter stages exhibit a lower sampling rate than does the at least one delta-sigma analog to digital converter stage.
7. The analog to digital converter of claim 1 , wherein the at least one delta-sigma analog to digital converter stage is a single stage.
8. The analog to digital converter of claim 7 , wherein the single delta-sigma analog to digital converter stage is an initial stage.
9. A method comprising:
processing a signal using an analog to digital converter, wherein the analog to digital converter comprises at least one delta-sigma analog to digital converter stage and a succession of pipelined analog to digital converter stages, wherein the pipelined analog to digital converter stages exhibit a sampling rate determined separately from that of the at least one delta-sigma analog to digital converter stage.
10. The method of claim 9 , wherein the sampling rates of the at least one delta-sigma analog to digital converter stage and the pipelined analog to digital converter stages are adjustable.
11. The method of claim 10 , wherein the sampling rate of each stage is adjusted by adjusting a sampling frequency of the stage.
12. The method of claim 9 , wherein the number of pipelined analog to digital converter stages is programmable.
13. The method of claim 9 , wherein the number of pipelined analog to digital converter stages is programmable based on the precision required to process the current signal.
14. The method of claim 9 , wherein the pipelined analog to digital converter stages exhibit a lower sampling rate than does the at least one delta-sigma analog to digital converter stage.
15. The method of claim 9 , wherein the at least one delta-sigma analog to digital converter stage is a single stage.
16. The method of claim 15 , wherein the single delta-sigma analog to digital converter stage is an initial stage.
17. An apparatus comprising:
means for processing a signal using an analog to digital converter, wherein the analog to digital converter comprises at least one delta-sigma analog to digital converter stage and a succession of pipelined analog to digital converter stages, wherein the pipelined analog to digital converter stages exhibit a sampling rate determined separately from that of the at least one delta-sigma analog to digital converter stage.
18. The apparatus of claim 17 , wherein the analog to digital converter comprises means for adjusting the sampling rates of the at least one delta-sigma analog to digital converter stage and the pipelined analog to digital converter stages.
19. The apparatus of claim 18 , wherein the means for adjusting the sampling rate of each stage comprises means for adjusting a sampling frequency of the stage.
20. The apparatus of claim 17 , wherein the analog to digital converter comprises means for programming the number of pipelined analog to digital converter stages.