All-digital delay-locked loop tuning method with randomized LSB-tuning
View Patent ↗In some example embodiments, there may be provided an apparatus. The apparatus may include a delay line including a plurality of cells; and tuning circuitry coupled to the delay line and configured to generate a first output and a second output to tune the delay of the delay line, wherein the first output tunes in aggregate the plurality of cells of the delay line, and wherein the second output tunes each of the plurality of cells separately. Related methods, systems, and articles of manufacture are also disclosed.
1. An apparatus comprising:
a digital delay line including a plurality of cells; and
a digital tuning circuitry, coupled to the digital delay line, configured to generate a first output and a second randomized output to digitally tune the delay of the digital delay line, wherein the first output digitally tunes in aggregate the plurality of cells of the digital delay line, and wherein the second randomized output digitally tunes an individual delay of each of the plurality of cells, of the digital delay line, separately.
2. The apparatus of claim 1 , wherein the second randomized output comprises at least one bit, wherein the at least one bit controls the tuning of at least one of the plurality of cells.
3. The apparatus of claim 1 , wherein the second randomized output comprises least significant bits, wherein each of the least significant bits controls a separate one of the plurality of cells.
4. The apparatus of claim 1 , wherein the second randomized output comprises least significant bits, wherein each of the least significant bits controls a separate one of the plurality of cells, wherein each of the least significant bits has a separate value.
5. The apparatus of claim 1 , wherein the second randomized output is scrambled.
6. The apparatus of claim 1 further comprising:
a phase detector, coupled to the tuning circuitry, to provide a control signal input to the tuning circuitry, wherein the second randomized output is generated based on the control signal input.
7. The apparatus of claim 1 , wherein at least one of a user equipment or a wireless access point includes the apparatus to enable generation of a signal, a local oscillator, and/or a clock.
8. A method comprising:
generating, at tuning circuitry, a first output;
generating, at the tuning circuitry, a second randomized output, wherein the tuning circuitry is coupled to a digital delay line including a plurality of cells;
a digital tuning, by the tuning circuitry, a delay of the digital delay line, the digital tuning performed based on the first output and the second randomized output, wherein the first output tunes in aggregate the plurality of cells of the digital delay line, and wherein the second randomized output tunes an individual delay of each of the plurality of cells, of the digital delay line, separately.
9. The method of claim 8 , wherein the second randomized output comprises at least one bit, wherein the at least one bit controls the tuning of at least one of the plurality of cells.
10. The method of claim 8 , wherein the second randomized output comprises least significant bits, wherein each of the least significant bits controls a separate one of the plurality of cells.
11. The method of claim 8 , wherein the second randomized output comprises least significant bits, wherein each of the least significant bits controls a separate one of the plurality of cells, wherein each of the least significant bits has a separate value.
12. The method of claim 8 , wherein the second randomized output is scrambled.
13. The method of claim 8 further comprising:
providing, by a phase detector coupled to the tuning circuitry, a control signal input to the tuning circuitry, wherein the second randomized output is generated based on the control signal input.
14. The method of claim 8 , wherein at least one of a user equipment or a wireless access point includes the tuning circuitry and the digital delay line to enable generation of a signal, a local oscillator, and/or a clock.
15. A non-transitory computer-readable storage medium including computer program code which when executed by at least one processor causes operations comprising:
generating, at tuning circuitry, a first output;
generating, at the tuning circuitry, a second randomized output, wherein the tuning circuitry is coupled to a delay line including a plurality of cells;
a digital tuning, by the tuning circuitry, a delay of the delay line, the digital tuning performed based on the first output and the second randomized output, wherein the first output digitally tunes in aggregate the plurality of cells of the delay line, and wherein the second randomized output digitally tunes each of the plurality of cells separately.
16. An apparatus comprising:
means for generating, at the apparatus, a first output;
means for generating, at the apparatus, a second randomized output, wherein the apparatus is coupled to a delay line including a plurality of cells;
means for digitally tuning, by the apparatus, a delay of the digital delay line, the digital tuning performed based on the first output and the second randomized output, wherein the first output digitally tunes in aggregate the plurality of cells of the digital delay line, and wherein the second randomized output digitally tunes an individual delay of each of the plurality of cells, of the digital delay line, separately.
17. The apparatus of claim 16 , wherein the second randomized output comprises at least one bit, wherein the at least one bit controls the tuning of at least one of the plurality of cells.
18. The apparatus of claim 16 , wherein the second randomized output comprises least significant bits, wherein each of the least significant bits controls a separate one of the plurality of cells.
19. The apparatus of claim 16 , wherein the second randomized output comprises least significant bits, wherein each of the least significant bits controls a separate one of the plurality of cells, wherein each of the least significant bits has a separate value.
20. The apparatus of claim 16 , wherein the second randomized output is scrambled.
21. The apparatus of claim 16 further comprising:
means for providing, by a phase detector coupled to the apparatus, a control signal input to the tuning circuitry, wherein the second randomized output is generated based on the control signal input.
22. The apparatus of claim 16 , wherein at least one of a user equipment or a wireless access point includes the apparatus to enable generation of a signal, a local oscillator, and/or a clock.
23. The apparatus of claim 1 , wherein the digital tuning circuitry includes a pseudorandom number generator configured to introduce random patterning to the second digital output.
24. The apparatus of claim 1 , wherein the tuning of the digital delay line is limited to digital tuning.