IP Library Patent Application 14466992
Patent Application
App. No. 14/466,992

HIGH YIELD SUBSTRATE ASSEMBLY

Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US None
App. No.
14/466,992
Abstract

High yield substrate assembly. In accordance with a first method embodiment, a plurality of piggyback substrates are attached to a carrier substrate. The edges of the plurality of the piggyback substrates are bonded to one another. The plurality of piggyback substrates are removed from the carrier substrate to form a substrate assembly. The substrate assembly is processed to produce a plurality of integrated circuit devices on the substrate assembly. The processing may use manufacturing equipment designed to process wafers larger than individual instances of the plurality of piggyback substrates.

Claims (28)

1 . An article of manufacture comprising:

a substrate assembly configured for formation of integrated circuit device structures thereon, said substrate assembly comprising:

a plurality of substrates bonded to one another on edges of said plurality of substrates, and

wherein said substrate assembly is configured for use with integrated circuit manufacturing equipment designed to process wafers larger than individual instances of said plurality of substrates.

2 . The article of manufacture of claim 1 wherein said substrate assembly has a width or diameter of 200 mm or greater.

3 . The article of manufacture of claim 1 wherein said substrate assembly is rectangular.

4 . The article of manufacture of claim 1 wherein instances of said plurality of substrates have a generally rectangular shape.

5 . The article of manufacture of claim 1 wherein instances of said plurality of substrates have a generally non-rectangular shape.

6 . The article of manufacture of claim 1 wherein bonds between said plurality of substrates comprise nano particles.

7 . The article of manufacture of claim 1 wherein bonds between said plurality of substrates comprise alumina.

8 . The article of manufacture of claim 1 wherein bonds between said plurality of substrates are operable to relieve thermal stress across said substrate assembly during said integrated circuit processing.

9 . The article of manufacture of claim 1 wherein at least one edge of one substrate of said plurality of substrates is not perpendicular to a face of said one substrate.

10 . The article of manufacture of claim 9 wherein said one edge enhances bonding of said one substrate in comparison to an edge that is perpendicular to a face of said one substrate.

11 . The article of manufacture of claim 1 wherein said plurality of substrates are from the set of substrates comprising sapphire (c − A1203), Gallium Nitride (GaN), Gallium Arsenide (GaAs), Gallium Phosphide (GaP), Lithium Tantalate (LiTa03), Lithium Niobate (LiNb03), Indium Arsenide (InAs), Indium Phosphide (InP), Silicon Carbide (SiC), and Germanium (Ge).

12 . An article of manufacture comprising:

a substrate having a surface,

wherein said surface comprises a plurality of structures formed thereon, and

wherein said plurality of structures are operable to relieve thermal stress across said substrate during integrated circuit processing.

13 . The article of manufacture of claim 12 wherein said plurality of structures interrupt a crystal structure of said surface.

14 . The article of manufacture of claim 12 wherein said structures comprise substrate material that is characterized as amorphous.

15 . The article of manufacture of claim 12 wherein said plurality of structures are void of substrate material.

16 . The article of manufacture of claim 12 wherein said plurality of structures are above said surface of said substrate.

17 . The article of manufacture of claim 12 wherein said plurality of structures are aligned in a rectilinear pattern on said surface.

18 . The article of manufacture of claim 12 wherein regions bounded by said plurality of structures comprise polygonal regions.

19 . The article of manufacture of claim 12 wherein regions bounded by said plurality of structures comprise a plurality of different shapes.

20 . The article of manufacture of claim 12 wherein said plurality of structures are configured to allow formation of a plurality of integrated circuit devices there between.

21 . The article of manufacture of claim 12 wherein said substrate is not substantially Silicon.

22 . The article of manufacture of claim 12 wherein said substrate is from the set of substrates comprising sapphire (crA1203), Gallium Nitride (GaN), Gallium Arsenide (GaAs), Gallium Phosphide (GaP), Lithium Tantalate (LiTaO3), Lithium Niobate (LiNb03), Indium Arsenide (InAs), Indium Phosphide (InP), Silicon Carbide (SiC), and Germanium (Ge).

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 25, 2014
From: WANG, LIANG; MOHAMMED, ILYAS; BEROZ, MASUD
To: INVENSAS CORPORATION
Reel/Frame 033822/0922 →