Semiconductor memory device, test control system, and method of operating test control system

1. A semiconductor memory device comprising:

a plurality of memory cells electrically coupled to a plurality of word lines; and

a word line failure detection unit suitable for supplying a test voltage to a test target word line selected from among the plurality of word lines, and for detecting the test voltage transferred from at least one of the plurality of word lines, wherein the at least one of the plurality of word lines except for the test target word line,

wherein the word line failure detection unit comprises:

a voltage supply section suitable for supplying the test voltage to the test target word line; and

a voltage detection section suitable for detecting the test voltage transferred through the at least one of the plurality of word lines,

wherein the word line failure detection unit is suitable for:

supplying the test voltage to the test target word line,

detecting the test voltage through the at least one of the plurality of word lines,

generating a detection signal based on the detected test voltage, and

obtaining failure information associated with the plurality of word lines in response to the detection signal.

2. A test control system comprising:

a semiconductor memory device comprising:

a memory bank including a plurality of word lines;

a word line failure detection unit suitable for supplying a test voltage to at least one first test target word line from among the plurality of word lines, and for detecting the test voltage through at least one second test target word line from among the plurality of word lines; and

a test control circuit suitable for selecting the at least one first test target word line and the at least one second test target word line,

wherein the word line failure detection unit comprises:

a voltage supply section suitable for supplying the test voltage to the at least one first test target word line; and

a voltage detection section suitable for detecting the test voltage through the at least one second test target word line,

wherein the at least one first test target word line is different from the at least one second test target word line, and the word line failure detection unit is suitable for:

supplying the test voltage to the at least one first test target word line;

detecting the test voltage through the at least one second test target word line; and

obtaining failure information on a status of electrical coupling between least two of the plurality of word lines in response to the detected test voltage.

3. The test control system of claim 2 , wherein the test control circuit is suitable for selecting the at least one first test target word line and the at least one second test target word line based on the failure information.

4. The test control system of claim 2 , wherein the test control circuit is suitable for determining a number of word lines in the at least one first test target word line and the at least one second test target word line based on the failure information.

5. A semiconductor memory device comprising:

a plurality of memory cells electrically coupled to a plurality of word lines; and

a word line failure detection unit suitable for supplying a test voltage to a test target word line selected from among the plurality of word lines, and for detecting the test voltage transferred from at least one of the plurality of word lines, wherein the at least one of the plurality of word lines except for the test target word line,

wherein the word line failure detection unit comprises:

a voltage supply section suitable for supplying the test voltage to the test target word line; and

a voltage detection section suitable for detecting a voltage level of the test target word line,

wherein the word line failure detection unit is suitable for:

supplying the test voltage to the test target word line,

detecting the voltage level of the test target word line after a predefined period of time,

generating a detection signal based on the detected voltage level, and

obtaining failure information associated with a status of electrical coupling between two or more of the plurality of word lines in response to the detection signal.

6. The test control system of claim 5 , wherein the test control circuit is suitable for determining a number word lines in the at least one first test target word line and the at least one second test target word line based on the failure information.

7. A test control system comprising:

a semiconductor memory device comprising:

a memory bank including a plurality of word lines;

a word line failure detection unit suitable for supplying a test voltage to at least one first test target word line from among the plurality of word lines, and for detecting the test voltage through at least one second test target word line from among the plurality of word lines; and

a test control circuit suitable for selecting the at least one first test target word line and the at least one second test target word line,

wherein the at least one first test target word line is substantially similar to the at least one second test target word line, and the word line failure detection unit is suitable for:

supplying the test voltage to the at least one first test target word line;

detecting a voltage level of the at least one second test target word line after a predefined period of time; and

obtaining failure information on a status of electrical coupling connection between at least two of the plurality of word lines based on the detected voltage level.

8. The test control system of claim 7 , wherein the test control circuit is suitable for resetting the at least one first test target word line and the at least one second test target word line based on the failure information.