Semiconductor memory device

1. A semiconductor memory device comprising:

a memory cell array;

a voltage generation circuit configured to generate a voltage applied to the memory cell array, the voltage generation circuit including a plurality of boosting circuits connected in series between an input terminal and an output terminal, and a switching circuit configured to short-circuit one or more of the boosting circuits to the input terminal; and

a control circuit configured to boost a voltage output from the output terminal at a first slope during a first period and to boost the voltage output from the output terminal at a second slope during a second period, the first slope being different from the second slope.

2. The device according to claim 1 , wherein the control circuit is configured to control a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array, and the switching circuit includes a first switch connected in parallel to a first group of boosting circuits between the input terminal and a first intermediate node, the first intermediate node being located between the input terminal and the output terminal.

3. The device according to claim 2 , wherein the switching circuit includes a second switch connected in parallel to a second group of boosting circuits that includes the first group of boosting circuits between the input terminal and a second intermediate node, the second intermediate node located between the first intermediate node and the output terminal.

4. The device according to claim 1 , further comprising:

a voltage detecting circuit configured to detect a voltage level at the output terminal,

wherein the control circuit increases the number of boosting circuits to be driven according to a detection result of the voltage detecting circuit, and

wherein the control circuit is configured to control a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array.

5. The device according to claim 4 ,

wherein the control circuit controls the conduction state of the switching circuit according to the detection result of the voltage detecting circuit.

6. The device according to claim 1 , further comprising:

a delay circuit configured to delay an input control signal,

wherein the control circuit increases the number of boosting circuits to be driven based on a signal output from the delay circuit, and

wherein the control circuit is configured to control a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array.

7. The device according to claim 6 ,

wherein the control circuit controls the conduction state of the switching circuit based on the signal output from the delay circuit.

8. A semiconductor memory device comprising:

a memory cell array;

a voltage generation circuit configured to generate a voltage applied to the memory cell array, the voltage generation circuit including a plurality of boosting circuits connected in series between an input terminal and an output terminal, and a plurality of switches, each of which has a first end connected to the input terminal and a second end connected to an intermediate node that is between two of the boosting circuits; and

a control circuit configured to boost a voltage output from the output terminal at a first slope during a first period and to boost the voltage output from the output terminal at a second slope during a second period, the first slope being different from the second slope.

9. The device according to claim 8 , wherein one or more of the boosting circuits that are between the intermediate node and the output terminal are driven to generate the voltage applied to the memory cell array regardless of the conduction state of the switches.

10. The device according to claim 8 , wherein the control circuit is configured to control a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array, and the switches includes a first switch connected in parallel to a first group of boosting circuits between the input terminal and a first intermediate node, the first intermediate node being located between the input terminal and the output terminal.

11. The device according to claim 10 , wherein the switches includes a second switch connected in parallel to a second group of boosting circuits that includes the first group of boosting circuits between the input terminal and a second intermediate node, the second intermediate node located between the first intermediate node and the output terminal.

12. The device according to claim 8 , further comprising:

a voltage detecting circuit configured to detect a voltage level at the output terminal,

wherein the control circuit increases the number of boosting circuits that are driven according to a detection result of the voltage detecting circuit, and

wherein the control circuit is configured to control a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array.

13. The device according to claim 12 ,

wherein the control circuit controls the conduction state of the switches according to the detection result of the voltage detecting circuit.

14. The device according to claim 8 , further comprising:

a delay circuit configured to delay an input control signal,

wherein the control circuit increases the number of boosting circuits that are driven based on a signal output from the delay circuit, and

wherein the control circuit is configured to control a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array.

15. The device according to claim 14 ,

wherein the control circuit controls the conduction state of the switches based on the signal output from the delay circuit.

16. A voltage generation method for a memory cell array of a semiconductor memory device, the method comprising:

driving a first group of boosting circuits connected in series between an input terminal and an output terminal during a first period;

driving a second group of boosting circuits connected in series between the input terminal and the output terminal during a second period after the first period, the second group of boosting circuits including the first group of boosting circuits;

driving a third group of boosting circuits connected in series between the input terminal and the output terminal during a third period after the second period, the third group of boosting circuits including the first and second groups of boosting circuits, and

boosting a voltage output from the output terminal at a first slope during the first period and boosting the voltage output from the output terminal at a second slope during a second period, the first slope being different from the second slope,

wherein one or more of the boosting circuits is coupled to a switching circuit that is configured to short-circuit the one or more of the boosting circuits to the input terminal.

17. The method according to claim 16 , wherein the first group of boosting circuits is driven in response to an input control signal.

18. The method according to claim 17 , further comprising:

detecting a voltage level at the output terminal, and

controlling a conduction state of the switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array,

wherein the second group of boosting circuits is driven when the voltage level is greater than a first voltage level, and the third group of boosting circuits is driven when the voltage level is greater than a second voltage level that is higher than the first voltage level.

19. The method according to claim 17 , further comprising:

delaying the input control signal, and

controlling a conduction state of a switching circuit to vary the number of boosting circuits that are driven to generate the voltage applied to the memory cell array,

wherein the second group of boosting circuits is driven based on the delayed input control signal.

20. The method according to claim 16 , further comprising:

detecting a voltage level at the output terminal,

wherein the third group of boosting circuits is driven when the voltage level reaches a predetermined voltage level.