Semiconductor memory device
View Patent ↗A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.
1. A nonvolatile semiconductor memory device comprising:
a first memory cell;
a second memory cell above the first memory cell;
a third memory cell above the second memory cell;
a first word line electrically connected to a gate of the first memory cell;
a second word line electrically connected to a gate of the second memory cell;
a third word line electrically connected to a gate of the third memory cell; and
a control unit configured to perform an erasing operation on the first memory cell, the second memory cell, and the third memory cell, wherein
during the erasing operation, the control unit applies a first voltage to the first word line, a second voltage different from the first voltage to the second word line, and a third voltage different from both the first voltage and the second voltage to the third word line.
2. The device according to claim 1 , further comprising:
a fourth memory cell above the third memory cell; and
a fourth word line electrically connected to a gate of the fourth memory cell, wherein
during the erasing operation, the control unit applies a fourth voltage different from the third voltage to the fourth word line.
3. The device according to claim 2 , wherein the third voltage is higher than the second voltage.
4. The device according to claim 2 , wherein the third voltage is lower than the second voltage.
5. The device according to claim 4 , further comprising:
a bit line and a source line electrically connected to opposite ends of a plurality of memory cells electrically connected in series, the memory cells including the first through fourth memory cells, wherein
during the erasing operation, the control unit applies voltages to erase the first and third memory cells and voltages to erase the second and fourth memory cells at different timings.
6. The device according to claim 5 , wherein the voltages applied by the control unit include a voltage applied to the bit line, a voltage applied to the source line, and voltages applied to the first through fourth word lines.
7. The device according to claim 6 , wherein different voltages are applied to the bit line and different voltages are applied to the source line at the different timings.
8. The device according to claim 6 , wherein the same voltages are applied to the bit line and the same voltages are applied to the source line at the different timings.
9. The device according to claim 1 , wherein,
during the erasing operation, after the control unit applies the first voltage to the first word line, the second voltage to the second word line, and the third voltage to the third word line, a first number of times, the control unit applies a fourth voltage higher than the first voltage to the first word line, a fifth voltage higher than the second voltage to the second word line, and a sixth voltage higher than the third voltage to the third word line.
10. The device according to claim 9 , wherein,
during the erasing operation, after the control unit applies the fourth voltage to the first word line, the fifth voltage to the second word line, and the sixth voltage to the third word line, a second number of times, the control unit determines that the erasing operation has failed.
11. A method of erasing memory cells of a nonvolatile semiconductor memory device that includes a first memory cell, a second memory cell above the first memory cell, a third memory cell above the second memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a third word line electrically connected to a gate of the third memory cell, said method comprising:
applying a first voltage to the first word line to erase the first memory cell;
applying a second voltage different from the first voltage to the second word line to erase the second memory cell; and
applying a third voltage different from both the first voltage and the second voltage to the third word line to erase the third memory cell.
12. The method according to claim 11 , wherein the nonvolatile semiconductor memory device further includes a fourth memory cell above the third memory cell, and a fourth word line electrically connected to a gate of the fourth memory cell, and the method further comprises:
applying a fourth voltage different from the third voltage to the fourth word line to erase the fourth memory cell.
13. The method according to claim 12 , wherein the third voltage is higher than the second voltage.
14. The method according to claim 12 , wherein the third voltage is lower than the second voltage.
15. The method according to claim 11 , further comprising:
applying a fourth voltage higher than the first voltage to the first word line a fifth voltage higher than the second voltage to the second word line, and a sixth voltage higher than the third voltage to the third word line, after the first voltage has been applied to the first word line, the second voltage to the second word line, and the third voltage to the third word line, a first number of times.
16. The method according to claim 15 , further comprising:
determining that erasing of the memory cells has failed, after the fourth voltage has been applied to the first word line, the fifth voltage to the second word line, and the sixth voltage to the third word line, a second number of times.
17. A method of erasing memory cells of a nonvolatile semiconductor memory device that includes a first memory cell, a second memory cell above the first memory cell, a third memory cell above the second memory cell, a fourth memory cell above the third memory cell, a first word line electrically connected to a gate of the first memory cell, and a second word line electrically connected to a gate of the second memory cell, a third word line electrically connected to a gate of the third memory cell, a fourth word line electrically connected to a gate of the fourth memory cell, and a bit line and a source line connected to opposite ends of memory cells connected in series, the serially connected memory cells including the first through fourth memory cells, said method comprising:
applying voltages to erase the first and third memory cells during a first time period of an erase operation; and
applying voltages to erase the second and fourth memory cells during a second time period of the erase operation that is after the first time period.
18. The method according to claim 17 , wherein the applied voltages include a voltage applied to the bit line, a voltage applied to the source line, and voltages applied to the first through fourth word lines.
19. The method according to claim 18 , wherein different voltages are applied to the bit line and different voltages are applied to the source line, during the first and second time periods.
20. The method according to claim 18 , wherein the same voltages are applied to the bit line and the same voltages are applied to the source line, during the first and second time periods.