Information processing device and semiconductor device
According to an embodiment, an information processing device includes a memory device, one or more peripheral devices, a processor, and a state controller. The processor is able to change between a first state, in which a command is executed, and a second state, in which an interrupt is awaited. When the processor enters the second state and if an operation for data transfer is being performed between at least one of the peripheral devices and the memory device, the state controller switches the information processing device to a third state in which power consumption is lower as compared to the first state. If the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the state controller switches the information processing device to a fourth state in which power consumption is lower as compared to the third state.
1. An information processing device comprising:
a memory device;
a second memory;
one or more peripheral devices;
a processor configured to execute a state controller, and to change between a first state, in which a command is executed by the processor, and a second state, in which an interrupt is awaited by the processor, wherein
when the processor enters the second state and an operation for data transfer is being performed between at least one of the peripheral devices and the memory device, the state controller switches the information processing device to a third state, the third state being a state in which power consumption of the information processing device is lower than power consumption of the information processing device when the processor is in the first state; and
when the processor enters the second state and an operation for data transfer is not being performed between any of the peripheral devices and the memory device, the state controller switches the information processing device to a fourth state, the fourth state being a state in which power consumption of the information processing device is lower than in the third state, and wherein
the memory device stores an operating system including the state controller and the second memory stores a switching program that switches the memory device from a power saving mode to a normal mode, and
the processor is configured to switch the memory device to the normal mode by executing the switching program when the processor changes from the second state to the first state, and the memory device is in the power saving mode.
2. The device according to claim 1 , wherein, in the fourth state, the state controller performs control to lower a voltage to be supplied to the processor.
3. The device according to claim 1 , wherein, in the fourth state, the state controller performs control to stop oscillation of a high-frequency oscillator that generates a high-frequency clock representing a clock used by the processor in the first state.
4. The device according to claim 1 , wherein, in the fourth state, the state controller performs control to stop power supply to a high-frequency oscillator that generates a high-frequency clock representing a clock used by the processor in the first state.
5. The device according to claim 3 , wherein the high-frequency oscillator is a silicon oscillator.
6. The device according to claim 4 , wherein the high-frequency oscillator is a silicon oscillator.
7. The device according to claim 1 , wherein
the memory device is a volatile memory, and
in the fourth state, the state controller performs control to switch the memory device to a self-refresh state in which it is possible to hold on to data stored in the memory device but it is not possible to perform data reading or data writing.
8. The device according to claim 1 , wherein
the memory device is a nonvolatile memory, and
in the fourth state, the state controller performs control to stop power supply to the memory device.
9. The device according to claim 1 , wherein
the processor includes a cache memory, and
when switching the information processing device to the fourth state, the state controller writes data, which is stored in the cache memory but which has not been written in the memory device, in the memory device and then perform control to stop power supply to the cache memory.
10. The device according to claim 1 , wherein
the processor includes a cache memory, and
in the fourth state, the state controller performs control to lower a voltage to be supplied to the cache memory than a voltage supplied when the processor is in the first state.
11. The device according to claim 1 , wherein the peripheral device is either one of a storage device, a communication device, a display device, and an image capturing device.
12. The device according to claim 1 , wherein the processor is configured to further execute a device controller controlling the peripheral devices,
upon receiving an input-output request from the processor, the device controller starts the operation for data transfer, and
when the operation for data transfer is completed, the device controller issues an interrupt as a notification to the processor.
13. The information processing device according to claim 1 , further comprising:
a microcomputer configured to have a lower processing performance and a lower power consumption than the processor, wherein
the microcomputer is configured to perform an interrupt handling operation if the interrupt is received from any of the peripheral devices connecting thereto, and transmit the interrupt to the processor, and the processor is configured to return from the second state to the first state.
14. An information processing method employed in an information processing device including a memory device, a second memory, one or more peripheral devices, and a processor configured to execute a state controller, and to change between a first state, in which a command is executed by the processor, and a second state, in which an interrupt is awaited by the processor, the information processing method comprising:
switching, by the state controller, when the processor enters the second state and an operation for data transfer is being performed between at least one of the peripheral devices and the memory device, the information processing device to a third state, the third state being a state in which power consumption of the information processing device is lower than power consumption of the information processing device when the processor is in the first state; and
switching, by the state controller, when the processor enters the second state and an operation for data transfer is not being performed between any of the peripheral devices and the memory device, the information processing device to a fourth state, the fourth state being a state in which power consumption of the information processing device is lower than in the third state, and wherein
the memory device stores an operating system including the state controller and the second memory stores a switching program that switches the memory device from a power saving mode to a normal mode, and
the processor is configured to switch the memory device to the normal mode by executing the switching program when the processor changes from the second state to the first state, and the memory device is in the power saving mode.
15. The method according to claim 14 , wherein, when the processor enters the second state, if the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the switching includes performing control to lower a voltage to be supplied to the processor.
16. The method according to claim 14 , wherein, when the processor enters the second state, if the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the switching includes performing control to stop oscillation of a high-frequency oscillator that generates a high-frequency clock representing a clock used by the processor in the first state.
17. The method according to claim 14 , wherein, when the processor enters the second state, the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the switching includes performing control to stop power supply to a high-frequency oscillator that generates a high-frequency clock representing a clock used by the processor in the first state.
18. The method according to claim 16 , wherein the high-frequency oscillator is a silicon oscillator.
19. The method according to claim 17 , wherein the high-frequency oscillator is a silicon oscillator.
20. The method according to claim 14 , wherein
the memory device is a volatile memory, and
when the processor enters the second state, the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the switching includes performing control to switch the memory device to a self-refresh state in which it is possible to hold on to data stored in the memory device but it is not possible to perform data reading or data writing.
21. The method according to claim 14 , wherein
the memory device is a nonvolatile memory, and
when the processor enters the second state, if the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the switching includes performing control to stop power supply to the memory device.
22. The method according to claim 14 , wherein
the processor includes a cache memory, and
when the processor enters the second state, if the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the switching includes writing data, which is stored in the cache memory but which has not been written in the memory device, in the memory device and then the processor performs control to stop power supply to the cache memory.
23. The method according to claim 14 , wherein
the processor includes a cache memory, and
when the processor enters the second state, if the operation for data transfer is not being performed between any of the peripheral devices and the memory device, the switching includes performing control to lower a voltage to be supplied to the cache memory below a voltage supplied to the cache memory when the processor is in the first state.
24. The method according to claim 14 , wherein the peripheral device is either one of a storage device, a communication device, a display device, and an image capturing device.
25. The method according to claim 14 , wherein the method further comprises: controlling a corresponding peripheral device, wherein
upon receiving an input-output request from the processor, the controlling includes starting the operation for data transfer, and
when the operation for data transfer is completed, the controlling includes issuing an interrupt as a notification to the processor.