IP Library Granted Patent US 9,113,152
Granted Patent B2
US 9,113,152 · App. 14/469,730 · Granted Aug 18, 2015

Frame block comparison

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Quick Facts
Patent No.
US 9,113,152
App. No.
14/469,730
Granted
Aug 18, 2015
Kind
B2
Abstract

Various arrangements for testing video decoder device functionality are presented. A video frame decoded by a video decoder device under test may be received. The received video frame may be segmented into a plurality of blocks. A first value may be calculated for a first block of the plurality of blocks of the received video frame using pixel values of pixels present within the first block. The first value may be compared to a first reference value. The first reference value may correspond to a first reference block of one or more reference frames. Video decoder functionality of the video decoder device may be determined to be functional at least partially based on comparing the first value to the first reference value.

Claims (50)

1. A method for determining functionality of a video decoder, comprising:

calculating, by a computer system, a pixel value for each pixel of a plurality of pixels of at least one pixel block of a decoded video frame, using a plurality of values each one associated with a particular sub-pixel of a corresponding pixel of the plurality of pixels;

calculating, by the computer system, a pixel block value using the pixel value for each of the plurality of pixels of the at least one pixel block; and

determining, by the computer system, that the video decoder is functioning within specification when the pixel block value substantially corresponds to a particular pixel block reference value.

2. The method of claim 1 , further comprising:

calculating the pixel value for each pixel of the plurality of pixels from a first sub-pixel color value, a second sub-pixel color value, and a third sub-pixel color value of a corresponding pixel.

3. The method of claim 1 , further comprising:

calculating the pixel block value from a summation of a first sub-pixel color value across each of the plurality of pixels, a summation of a second sub-pixel color value across each of the plurality of pixels, and a summation of a third sub-pixel color value across each of the plurality of pixels.

4. The method of claim 1 , further comprising:

calculating the pixel block value from an average of a first sub-pixel color value across each of the plurality of pixels, an average of a second sub-pixel color value across each of the plurality of pixels, and an average of a third sub-pixel color value across each of the plurality of pixels.

5. The method of claim 1 , further comprising:

determining that the video decoder is functioning within specification when the pixel block value is matched to the particular pixel block reference value.

6. The method of claim 1 , further comprising:

determining that the video decoder is functioning within specification when the pixel block value is within a threshold range of the particular pixel block reference value.

7. The method of claim 1 , further comprising:

determining that the pixel block value substantially corresponds to the particular pixel block reference value; and

outputting, by the computer system, an indication that the video decoder is functioning within specification.

8. The method of claim 1 , further comprising:

calculating a pixel value for each pixel of an N×N block of pixels of the at least one pixel block, wherein N is an integer value.

9. The method of claim 1 , further comprising:

calculating a pixel value for each pixel of an M×N, or N×M, block of pixels of the at least one pixel block, wherein N and M are non-equal integer values.

10. A system for determining functionality of a video decoder, comprising:

a processor and a memory, wherein the memory is communicatively coupled with and readable by the processor and having stored therein processor-readable and non-transient instructions which, when executed by the processor, cause the system to:

calculate a pixel value for each pixel of a plurality of pixels of at least one pixel block of a decoded video frame, using a plurality of values each one associated with a particular sub-pixel of a corresponding pixel of the plurality of pixels;

calculate a pixel block value using the pixel value for each of the plurality of pixels of the at least one pixel block; and

determine that the video decoder is functioning within specification when the pixel block value substantially corresponds to a particular pixel block reference value.

11. The system of claim 10 , wherein the processor-readable and non-transient instructions when executed by the processor cause the system to:

calculate the pixel value for each pixel of the plurality of pixels from a first sub-pixel color value, a second sub-pixel color value, and a third sub-pixel color value of a corresponding pixel.

12. The system of claim 10 , wherein the processor-readable and non-transient instructions when executed by the processor cause the system to:

calculate the pixel block value from a summation of a first sub-pixel color value across each of the plurality of pixels, a summation of a second sub-pixel color value across each of the plurality of pixels, and a summation of a third sub-pixel color value across each of the plurality of pixels.

13. The system of claim 10 , wherein the processor-readable and non-transient instructions when executed by the processor cause the system to:

calculate the pixel block value from an average of a first sub-pixel color value across each of the plurality of pixels, an average of a second sub-pixel color value across each of the plurality of pixels, and an average of a third sub-pixel color value across each of the plurality of pixels.

14. The system of claim 10 , wherein the processor-readable and non-transient instructions when executed by the processor cause the system to:

determine that the video decoder is functioning within specification when the pixel block value is matched to the particular pixel block reference value.

15. The system of claim 10 , wherein the processor-readable and non-transient instructions when executed by the processor cause the system to:

determine that the video decoder is functioning within specification when the pixel block value is within a threshold range of the particular pixel block reference value.

16. The system of claim 10 , wherein the processor-readable and non-transient instructions when executed by the processor cause the system to:

determine that the pixel block value substantially corresponds to the particular pixel block reference value; and

output an indication that the video decoder is functioning within specification.

17. The system of claim 10 , wherein the processor-readable and non-transient instructions when executed by the processor cause the system to:

calculate a pixel value for each pixel of an N×N block of pixels of the at least one pixel block, wherein N is an integer value.

18. The system of claim 10 , wherein the processor-readable and non-transient instructions when executed by the processor cause the system to:

calculate a pixel value for each pixel of an M×N or an N×M block of pixels of the at least one pixel block, wherein N and M are non-equal integer values.

19. A computer program product residing on a non-transitory processor-readable medium, the computer program product comprising processor-readable instructions to cause one or more processors to:

calculate a pixel value for each pixel of a plurality of pixels of at least one pixel block of a decoded video frame, using a plurality of values each one associated with a particular sub-pixel of a corresponding pixel of the plurality of pixels;

calculate a pixel block value using the pixel value for each of the plurality of pixels of the at least one pixel block; and

determine that a video decoder that generated the decoded video frame is functioning within specification when the pixel block value substantially corresponds to a particular pixel block reference value.

20. The computer program product of claim 19 , wherein the computer program product comprising processor-readable instructions to cause the one or more processors to:

determine that the pixel block value substantially corresponds to the particular pixel block reference value; and

output an indication that the video decoder is functioning within specification.

Assignments (2)
SECURITY INTEREST Recorded Nov 30, 2021
From: DISH BROADCASTING CORPORATION; DISH NETWORK L.L.C.; DISH TECHNOLOGIES L.L.C.
To: U.S. BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 058295/0293 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2014
From: VALDEZ, JASON; KUNZE, WAYNE
To: DISH NETWORK L.L.C.
Reel/Frame 034593/0292 →