IP Library Granted Patent US 9,105,534
Granted Patent B2
US 9,105,534 · App. 14/469,752 · Granted Aug 11, 2015

Semiconductor device, method of manufacturing thereof, circuit board and electronic apparatus

Inventor: Haruki Ito (Chino, JP)
Assignee: Seiko Epson Corporation
H01L24/14H01L23/3114H01L23/49816H01L24/17H01L2224/13014H01L2224/14131H01L2224/16225H01L2924/0002H01L2924/013H01L2924/014H01L2924/01022H01L2924/01029H01L2924/01074H01L2924/186
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,105,534
App. No.
14/469,752
Granted
Aug 11, 2015
Kind
B2
Abstract

A semiconductor device is provided comprising: a semiconductor element including a plurality of electrodes; first wirings coupled to the electrodes and directed toward a center of the semiconductor element from a portion coupled to the electrodes; second wirings coupled between the first wirings and external terminals, the second wirings being directed to an outer area of the semiconductor element relative to the center; and at least one resin layer formed between the first wirings and the second wirings.

Claims (39)

1. A semiconductor device comprising:

a substrate;

a first electrode;

a second electrode;

a first terminal that is electrically connected to the first electrode;

a second terminal that is electrically connected to the second electrode;

a first wiring that is electrically connected to the first electrode and the first terminal;

a second wiring that is electrically connected to the second electrode and the second terminal; and

a first insulating layer that is disposed between the first wiring and the substrate, and that is disposed between the second wiring and the substrate,

wherein the first wiring covers a first step of the first insulating layer,

the first and second electrodes are formed along a circumference of the substrate,

the first and second wirings each include a first portion and a second portion that are separated by the first insulation layer,

locations of the first and second terminals are located more circumferentially outward than locations where the first portions connect with the second portions, and

the second wiring covering a second step of the first insulating layer.

2. The semiconductor device according to claim 1 ,

the first insulating layer containing a resin.

3. The semiconductor device according to claim 1 , further comprising:

a second insulating layer that is disposed so as to cover the first wiring and the second wiring.

4. The semiconductor device according to claim 3 ,

the second insulating layer containing a resin.

5. The semiconductor device according to claim 1 , further comprising:

a third electrode;

a third terminal that is electrically connected to the third electrode;

a third wiring that is electrically connected to the third electrode and the third terminal,

the third wiring covering a third step of the first insulating layer,

the third wiring being disposed between the first terminal and the second terminal.

6. The semiconductor device according to claim 1 , further comprising:

a third insulating layer that is disposed so as to cover the second insulating layer.

7. The semiconductor device according to claim 1 ,

the third insulating layer containing a resin.

8. The semiconductor device according to claim 1 ,

the first step and the second step being continuous.

9. The semiconductor device according to claim 8 ,

the first step and the second step extending along to a first direction, the first electrode and the second electrode being arranged along to the first direction.

10. The semiconductor device according to claim 1 ,

the first step being disposed between the first electrode and the first terminal,

the second step being disposed between the second electrode and the second terminal.

11. An electronic apparatus comprising the semiconductor device according to claim 1 .

12. The semiconductor device according to claim 1 , further comprising a via hole formed at the locations where the first portions connect with the second portions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 4, 2019
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 050265/0622 →
Priority Claims (1)
JP 2003-419406 · Dec 17, 2003 · national
Continuity (5)
Continuation 13908531 · Jun 3, 2013
Continuation 13156686 · Jun 9, 2011
Continuation 12569478 · Sep 29, 2009
Division 11016504 · Dec 17, 2004
Related Publication 20140361434A1 · Dec 11, 2014