IP Library Granted Patent US 10,402,305
Granted Patent B2
US 10,402,305 · App. 14/469,837 · Granted Sep 3, 2019

Computer and compiling method

Inventors: Tsuyoshi Nagao (Kawasaki, JP); Shuji Satoh (Kawasaki, JP); Hitoshi Suzuki (Kawasaki, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
G06F11/3636G06F9/30032G06F9/30076G06F11/3656
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 10,402,305
App. No.
14/469,837
Granted
Sep 3, 2019
Kind
B2
Abstract

To provide new instruction and device suitable for tracing execution of a computer program. In an embodiment, a CPU is configured so as to supply a constant to a trace unit in response to decoding of a first instruction having an immediate field indicating the constant. In addition, the trace unit is configured so as to output trace data including the constant in response to execution of the first instruction in the CPU.

Claims (28)

1. A computer system, comprising:

a CPU (Central Processing Unit); and

a trace unit coupled to the CPU,

wherein the CPU is configured so as to:

sequentially retrieve and decode instructions of a sequence of instructions comprising a computer program being executed by the CPU from a memory accessible by the CPU; and

for each retrieved and decoded instruction, analyze an operation code of the retrieved and decoded instruction to determine whether the instruction comprises a tracing operation instruction as a high-level computer language instruction that can be selectively and arbitrarily embedded as a high-level computer language instruction into the computer program stored in the memory as a high-level computer program to be retrieved, decoded, compiled, and executed by the CPU, the tracing operation instruction comprising a first field and a second field, the first field comprising a tracing operation instruction code and the second field comprising an immediate field for indicating a value of a constant that provides an identifier unique to each of an execution instance of the tracing operation instruction,

wherein:

if the retrieved and decoded instruction is determined not to be the tracing operation instruction, then the CPU executes an operation other than tracing, as indicated by whatever operation code other than tracing is included in the retrieved, decoded, and compiled instruction, and

if the retrieved and decoded instruction is determined to be the tracing operation instruction, then the CPU supplies the constant in the immediate field to the trace unit as the identifier for instructions to be traced as a result of the tracing operation instruction being embedded in the computer program, based on information in the immediate field,

wherein the trace unit is configured so as to output trace data, including the constant, in response to execution of the tracing operation instruction in the CPU, as a tracing operation within the computer program being executed by the CPU, the constant from the immediate field of the tracing operation instruction thereby providing an identifier unique to the tracing operation initiated by the tracing operation instruction, and

wherein the CPU further supplies a value of a program counter (PC) to the trace unit as a result of compiling the tracing operation instruction.

2. The computer system according to claim 1 , wherein the constant indicates an identifier of a function, a thread, a process, or a task, included in the computer program being executed by the CPU.

3. The computer system according to claim 2 , wherein the tracing operation instruction is arranged by a compiler in any of immediately before an instruction group of the function, the thread, the process, or the task, in the instruction group, or immediately after the instruction group, in the program.

4. The computer system according to claim 1 , wherein the tracing operation instruction does not include a register field for specifying a register operand.

5. The computer system according to claim 1 , wherein the tracing operation instruction includes only one instruction when compiled as an instruction.

6. The computer system according to claim 1 , wherein the CPU includes a plurality of general-purpose registers specified as a register operand in an instruction executed by the CPU, and

the CPU supplies the constant to the trace unit without storing the constant in the general-purpose registers in an execution of the tracing operation instruction.

7. The computer system according to claim 1 , wherein the CPU includes:

an instruction decode and dispatch unit;

an execution unit;

a plurality of general-purpose registers versatilely used in order to temporarily store data inputted into the execution unit and data outputted from the execution unit; and

a completion unit,

wherein the instruction decode and dispatch unit are configured so as to supply the constant indicated in the immediate field to the execution unit in response to decoding and compiling of the tracing operation instruction,

wherein the execution unit is configured so as to supply the constant to the completion unit without storing the constant in the general-purpose registers in an execution of the tracing operation instruction, and

wherein the completion unit is configured so as to supply an execution result of the tracing operation instruction including the constant to the trace unit.

8. The computer system according to claim 1 , wherein the trace data further includes an address of the tracing operation instruction.

9. The computer system according to claim 1 , wherein the trace unit includes a filter circuit that filters the constant on the basis of a first condition and that selectively outputs the constant as the trace data on a condition that the constant coincides with the first condition.

10. The computer system according to claim 1 , wherein information can be selectively inserted into the second field of the tracing operation instruction as a part of embedding the tracing operation instruction into the high-level computer program.

Assignments (2)
CHANGE OF ADDRESS Recorded Dec 18, 2017
From: RENESAS ELECTRONICS CORPORATION
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 045764/0902 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2014
From: NAGAO, TSUYOSHI; SATOH, SHUJI; SUZUKI, HITOSHI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 033633/0195 →
Priority Claims (1)
JP 2013-203680 · Sep 30, 2013 · national
Continuity (1)
Related Publication 20150095715A1 · Apr 2, 2015