Methods and systems for improving light load efficiency for power stages of multi-phase voltage regulator circuits
Methods and systems are disclosed that may be employed to improve efficiency of smart integrated power stages (IPstages) of multi-phase VR systems while operating under relatively light, ultra-light, or partial or reduced loads. The disclosed methods and systems may be implemented to improve VR system light load efficiency by providing and enabling reduced power IPstage operating modes in one or more smart IPstage/s of a VR system, and by enabling state transition between IPstage active and reduced power operating modes such as IPstage standby and IPstage hibernation modes.
1. A system, comprising:
at least one integrated power stage (IPstage) comprising an IPstage processing device, power-consuming circuitry, and a power output;
where the power output of the IPstage is configured to be coupled to a bootstrap capacitor;
where the IPstage is configured to be coupled to receive signals from a separate processing device configured as a voltage regulator (VR) controller that command the IPstage to selectively provide or not provide power to the power output of the IPstage; and
where the IPstage processing device is configured to:
monitor voltage on the bootstrap capacitor while the IPstage is commanded by a coupled VR controller to not provide power to the power output of the IP stage,
enter an IPstage stand-by mode by turning off at least a first portion of the power-consuming circuitry of the IPstage when the monitored voltage of a coupled bootstrap capacitor becomes less than or equal to a pre-determined standby voltage (V standBy ) threshold value while the IPstage is not providing power to the power output of the IPstage in response to a command from the VR controller, and
then exit the stand-by mode by turning on the at least first portion of the power-consuming circuitry of the IPstage when the IPstage receives a command from the VR controller to provide power to the power output of the IPstage.
2. The system of claim 1 , where the power-consuming circuitry of the IPstage comprises at least one of current sense circuitry configured to sense output current from the IPstage power output, half-bridge power circuitry configured to provide output power to the IPstage power output, gate driver circuitry configured to drive the half-bridge power circuitry, or a combination thereof.
3. The system of claim 1 , where the IPstage processing device is configured to:
monitor voltage on the bootstrap capacitor while the IPstage is commanded by the VR controller to not provide power to the power output of the IP stage; and
control at least a second portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage;
where the Y bootMin threshold value is less than the V standBy threshold value.
4. The system of claim 3 , where the IPstage processing device is configured to:
control the at least second portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage; and
then control the at least second portion of the power-consuming circuitry of the IPstage to stop supplying current to the bootstrap capacitor when the monitored voltage of the bootstrap capacitor increases to greater than or equal to pre-determined maximum Vboot Refresh (V bootMax ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage.
5. The system of claim 3 , where the IPstage is further configured to receive a hibernation activation signal from the VR controller controller; and where the IPstage processing device is configured to respond to the hibernation activation signal and enter an IPstage hibernation mode by turning off at least the second portion of the power-consuming circuitry of the IPstage in addition to the first portion of the power-consuming circuitry of the IPstage such that the bootstrap capacitor is not refreshed during the duration of the IPstage hibernation mode.
6. The system of claim 5 , where the IPstage is further configured to receive a hibernation deactivation signal from the VR controller controller; and where the IPstage processing device is configured to respond to the hibernation deactivation signal and exit the IPstage hibernation mode to an active power regulation mode by turning on the first and second portions of the power-consuming circuitry of the IPstage.
7. The system of claim 6 , where the IPstage is configured to be coupled to the VR controller by a bi-directional power device identification signal path that is configured to communicate signals between the IPstage and the VR controller that are indicative of the identity of the IPstage; and where the IPstage is further configured to recognize a first signal on the power device identification signal path from the VR controller controller as the hibernation activation signal; and to recognize a second signal on the power device identification signal path from the VR controller controller as the hibernation deactivation signal.
8. The system of claim 3 , where the at least first portion of the power-consuming circuitry comprises the current sense circuitry; where the at least second portion of the power-consuming circuitry of the IPstage of the IPstage comprises at least a portion of half-bridge power circuitry configured to provide output power to the IPstage power output; and where the IPstage processing device is configured to control the at least a portion of the half-bridge power circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to the pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage.
9. A method of operating a voltage regulator (VR) system that includes at least one processing device, comprising:
using the at least one processing device as a voltage regulator (VR) controller to control operation of at least one integrated power stage (IPstage) of the VR system, the IPstage having a separate IPstage processing device, power-consuming circuitry, and a power output that is coupled to a bootstrap capacitor;
using the VR controller to provide signals to the IPstage to command the IPstage to selectively provide or not provide power to the power output of the IPstage; and
using the IPstage processing device to:
monitor voltage on the bootstrap capacitor while the IPstage is commanded by the VR controller to not provide power to the power output of the IP stage,
enter an IPstage stand-by mode by turning off at least a first portion of the power-consuming circuitry of the IPstage when the monitored voltage of a coupled bootstrap capacitor becomes less than or equal to a pre-determined standby voltage (V standBy ) threshold value while the IPstage is not providing power to the power output of the IPstage in response to a command from the VR controller, and
then exit the stand-by mode by turning on the at least first portion of the power-consuming circuitry of the IPstage when the IPstage receives a command from the VR controller to provide power to the power output of the IPstage.
10. The method of claim 9 , where the power-consuming circuitry of the IPstage comprises at least one of current sense circuitry configured to sense output current from the IPstage power output, half-bridge power circuitry configured to provide output power to the IPstage power output, gate driver circuitry configured to drive the half-bridge power circuitry, or a combination thereof.
11. The method of claim 9 , further comprising using the IPstage processing device to:
monitor voltage on the bootstrap capacitor while the IPstage is commanded by the VR controller to not provide power to the power output of the IP stage; and
control at least a second portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (Y bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage;
where the V bootMin threshold value is less than the V standBy threshold value.
12. The method of claim 11 , further comprising using the IPstage processing device to:
control the at least second portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (Y bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage; and
then control the at least second portion of the power-consuming circuitry of the IPstage to stop supplying current to the bootstrap capacitor when the monitored voltage of the bootstrap capacitor increases to greater than or equal to pre-determined maximum Vboot Refresh (V bootMax ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage.
13. The method of claim 11 , further comprising providing a hibernation activation signal from the VR controller controller to the IPstage; and using the IPstage processing device to respond to the hibernation activation signal and enter an IPstage hibernation mode by turning off at least the second portion of the power-consuming circuitry of the IPstage in addition to the first portion of the power-consuming circuitry of the IPstage such that the bootstrap capacitor is not refreshed during the duration of the IPstage hibernation mode.
14. The method of claim 13 , further comprising providing a hibernation deactivation signal from the VR controller controller to the IPstage; and using the IPstage processing device to respond to the hibernation deactivation signal and exit the IPstage hibernation mode to an active power regulation mode by turning on the first and second portions of the power-consuming circuitry of the IPstage.
15. The method of claim 14 , where the IPstage is coupled to the VR controller by a bi-directional power device identification signal path; and where the method further comprises:
communicating signals between the IPstage and the VR controller that are indicative of the identity of the IPstage; and
providing a first signal on the power device identification signal path from the VR controller controller to the IPstage as the hibernation activation signal; and
providing a second signal on the power device identification signal path from the VR controller controller to the IPstage as the hibernation activation signal.
16. The system of claim 11 , where the at least first portion of the power-consuming circuitry comprises the current sense circuitry; where the at least second portion of the power-consuming circuitry of the IPstage of the IPstage comprises at least a portion of half-bridge power circuitry configured to provide output power to the IPstage power output; and where the method further comprises using the IPstage processing device to control the at least a portion of the half-bridge power circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to the pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage.
17. A voltage regulator (VR) system, comprising:
at least one integrated power stage (IPstage) comprising an IPstage processing device, power-consuming circuitry, and a power output coupled to a bootstrap capacitor;
at least one processing device configured as a VR system controller coupled to control the IPstage to selectively provide or not provide power to the power output of the IPstage; and
where the IPstage processing device is configured to:
monitor voltage on the bootstrap capacitor while the IPstage is controlled by the VR controller to not provide power to the power output of the IP stage,
enter an IPstage stand-by mode by turning off at least a first portion of the power-consuming circuitry of the IPstage when the monitored voltage of a coupled bootstrap capacitor becomes less than or equal to a pre-determined standby voltage (V standBy ) threshold value while the IPstage is controlled to not provide power to the power output of the IPstage by the VR controller, and
then exit the stand-by mode by turning on the at least first portion of the power-consuming circuitry of the IPstage when the IPstage is controlled by the VR controller to provide power to the power output of the IPstage.
18. The system of claim 17 , where the IPstage processing device is configured to:
monitor voltage on the bootstrap capacitor while the IPstage is commanded by the VR controller to not provide power to the power output of the IP stage; and
control at least a second portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage;
where the V bootMin threshold value is less than the V standBy threshold value.
19. The system of claim 18 , where the IPstage processing device is configured to:
control the at least second portion of the power-consuming circuitry of the IPstage to supply current to the bootstrap capacitor to increase voltage on the bootstrap capacitor when the monitored voltage of the bootstrap capacitor becomes less than or equal to a pre-determined refresh voltage (V bootMin ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage; and
then control the at least second portion of the power-consuming circuitry of the IPstage to stop supplying current to the bootstrap capacitor when the monitored voltage of the bootstrap capacitor increases to greater than or equal to pre-determined maximum Vboot Refresh (V bootMax ) threshold value while the IPstage processing device is not providing power to the power output of the IPstage.
20. The system of claim 18 , where the VR controller is further configured to provide a hibernation activation signal to the IPstage; where the IPstage processing device is configured to respond to the hibernation activation signal and enter an IPstage hibernation mode by turning off at least the second portion of the power-consuming circuitry of the IPstage in addition to the first portion of the power-consuming circuitry of the IPstage such that the bootstrap capacitor is not refreshed during the duration of the IPstage hibernation mode; where the VR controller is further configured to provide a hibernation deactivation signal to the IPstage; and where the IPstage processing device is configured to respond to the hibernation deactivation signal and exit the IPstage hibernation mode to an active power regulation mode by turning on the first and second portions of the power-consuming circuitry of the IPstage.
21. The system of claim 17 , where the VR controller being configured to:
first control the IPstage to selectively not provide power to the power output of the IPstage by sending a phase-shedding command signal to the IPstage; and
then control the IPstage to selectively provide power to the power output of the IPstage by sending a wakeup command signal to the IPstage.