IP Library › Granted Patent US 9,787,172

Granted Patent B2

US 9,787,172 · App. 14/470,455 · Granted Oct 10, 2017

Methods and systems for implementing adaptive FET drive voltage optimization for power stages of multi-phase voltage regulator circuits

Inventors: Shiguo Luo (Austin, TX); Ralph H. Johnson (Round Rock, TX)

Assignee: Dell Products LP

H02M1/084 H02M1/08 H02M3/157 H02M3/1584 G06F1/26

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Quick Facts

Patent No.: US 9,787,172
App. No.: 14/470,455
Granted: Oct 10, 2017
Kind: B2

External Links

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Abstract

Methods and systems are disclosed that may be employed to implement adaptive FET drive voltage optimization for voltage regulator (VR) integrated power stages (IPstages) that have different MOSFET RDS(on) characteristics to improve VR efficiency and current-sense accuracy.

Claims (149)

1. A system, comprising:

at least one integrated power stage (IPstage) comprising a voltage input, a voltage output, one or more field effect transistor (FET) switching devices coupled between the voltage input and the voltage output to provide regulated power to the voltage output, and an IPstage identification (ID) recognition module having a power device identification signal output that is indicative of an identity of the at least one IPstage;

at least one processing device coupled to control operation of the at least one IPstage, the at least one, processing device also being coupled to receive the power device identification signal output from the at least one IPstage;

a power stage gate drive voltage regulator (VR) coupled between the at least one processing device and the at least one IPstage, the power stage gate drive VR being configured to provide a regulated gate drive voltage to drive the FET switching devices of the at least one IPstage;

where the at least one processing device is configured to:

receive the power device identification signal output from the at least one IPstage,

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

provide the FET drive voltage control signal to control the power stage gate drive VR to provide a determined FET drive voltage to drive the FET switching devices of the at least one IPstage while controlling the at least one IPstage to provide power to the voltage output;

where the at least one processing device coupled to control operation of the at least one IPstage is configured as a VR system controller;

where the system further comprises memory accessible by the VR system controller having information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage stored thereon together with information indicative of FET drive voltage control signal values for different types of IPstages;

where the VR system controller is also coupled to receive the power device identification signal output from the at least one IPstage with the power stage gate drive VR being coupled between the VR system controller and the at least one IPstage; where the memory comprises external non-volatile memory (NVM) coupled to the VR system controller, the NVM storing information indicative of FET drive voltage control signal values corresponding to multiple different types of IPstages that include the at least one IPstage; and

where the VR controller is further configured to:

receive the power device identification signal output from the at least one IPstage,

determine the identity of the at least one IPstage based on the received power device identification signal,

retrieve information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage from the NVM, and

provide the indicated FET drive voltage control signal value to the power stage gate drive VR; and

where the power stage gate drive VR is configured to provide a regulated gate drive voltage based on the value of the retrieved FET drive voltage control signal provided by the VR controller to drive a gate of the FET switching devices of the at least one IPstage while the VR controller controls the at least one IPstage to provide power to the voltage output.

2. A system, comprising:

at least one processing device coupled to control operation of the at least one IPstage, the at least one processing device also being coupled to receive the power device identification signal output from the at least one IPstage;

where the at least one processing device is configured to:

receive the power device identification signal output from the at least one IPstage;

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

where the at least one processing device coupled to control operation of the at least one IPstage is configured as a VR system controller;

where the VR system controller is also coupled to receive the power device identification signal output from the at least one IPstage with the power stage gate drive VR being coupled between the VR system controller and the at least one IPstage; where the memory comprises an internal memory register of the VR system controller that stores information indicative of FET drive voltage control signal values corresponding to multiple different types of IPstages that include the at least one IPstage; and

where the VR controller is further configured to:

receive the power device identification signal output from the at least one IPstage,

determine the identity of the at least one IPstage based on the received power device identification signal,

retrieve information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage from the internal memory register, and

provide the indicated FET drive voltage control signal value to the power stage gate drive VR; and

where the power stage gate drive VR is configured to provide a regulated gate drive voltage based on the value of the retrieved FET drive voltage control signal provided by the VR controller to drive the gate of the FET switching devices of the at least one IPstage while the VR controller controls the at least one IPstage to provide power to the VR system voltage output.

3. The system of claim 2 , where the FET switching devices comprise MOSFET switching devices.

4. A system, comprising:

where the at least one processing device is configured to:

receive the power device identification signal output from the at least one IPstage,

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

provide the FET drive voltage control signal to control the power stage gate drive VR to provide a determined FET drive voltage to drive the FET switching devices of the at least one IP stage while controlling the at least one IPstage to provide power to the voltage output;

where the at least one processing device coupled to control operation of the at least one IPstage is configured as a VR system controller;

where each of the multiple different types of IPstages has different drain to source resistance in on-state characteristics as a function of gate drive voltage or gate-to-source voltage; and where the VR system controller is configured to identify and retrieve the information indicative of a FET drive voltage control signal value that corresponds to the identified type of IPstage from the memory.

5. A system, comprising:

where the at least one processing device is configured to:

receive the power device identification signal output from the at least one IPstage,

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

where the at least one processing device coupled to control operation of the at least one IPstage is configured as a VR system controller; where the VR system controller comprises an internal memory register configured to receive and store the power device identification signal output from the at least one IPstage; where each of the VR system controller and the power stage gate drive VR are configured to be coupled to at least one separate external processing device; where the VR system controller is configured to provide the at least one external processing device with access to the power device identification signal output from the at least one IPstage stored in the internal memory register; and where the power stage gate drive VR is configured to receive a FET drive voltage control signal value from the at least one external processing device that is based at least in part on information indicative of a FET drive voltage control signal value that corresponds to the identified type of IPstage retrieved from internal register of the VR controller by the at least one external processing device.

6. The system of claim 5 , further comprising the at least one external processing device; and where the at least one external processing device is configured to:

retrieve the stored IPstage power device identification signal output from the internal memory register of the VR system controller;

determine a FET drive voltage control signal value based at least in part on the received power device identification signal; and

provide the determined FET drive voltage control signal value to control the power stage gate drive VR to provide a determined FET drive voltage to drive the FET switching devices of the at least one IPstage.

7. The system of claim 6 , where the at least one external processing device is service processor or a host CPU processing device executing system basic input/output system (BIOS).

8. A method of operating a voltage regulator (VR) system using at least one processing device, comprising:

using the at least one processing device to control operation of at least one integrated power stage (IPstage) to provide regulated power to a voltage output of the VR system, the at least one IPstage also including a voltage input, and one or more field effect transistor (FET) switching devices coupled between the voltage input and the voltage output;

using the at least one processing device to:

receive a power device identification signal output from the at least one IPstage that is indicative of the identity of the at least one IPstage,

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

provide the FET drive voltage control signal to a power stage gate drive VR;

using the power stage gate drive VR to provide a determined regulated FET drive voltage based on the FET drive voltage control signal to drive the FET switching devices of the at least one IPstage while using the at least one processing device to control the at least one IPstage to provide power to the voltage output; and

using the at least one processing device as a VR controller to identify and retrieve information indicative of a FET drive voltage control signal value that corresponds to the identified type of IPstage from memory accessible by the VR controller;

where the memory comprises non-volatile memory (NVM); and where the method further comprises:

using the at least one processing device as a VR controller to:

control operation of the at least one IPstage to provide regulated power to a voltage output of the VR system,

receive the power device identification signal output from the at least one IPstage,

determine the identity of the at least one IPstage based on the received power device identification signal,

retrieve information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage from the non-volatile memory (NVM) coupled to the VR controller,

provide the indicated FET drive voltage control signal value to the power stage gate drive VR; and

using the power stage gate drive VR to provide a regulated gate drive voltage based on the value of the retrieved FET drive voltage control signal provided by the VR controller to drive the gate of the FET switching devices of the at least one IPstage while using the VR controller to control the at least one IPstage to provide power to the VR system voltage output.

9. A method of operating a voltage regulator (VR) system using at least one processing device, comprising:

using the at least one processing device to:

receive a power device identification signal output from the at least one IPstage that is indicative of the identity of the at least one IPstage,

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

provide the FET drive voltage control signal to a power stage gate drive VR;

where the memory comprises an internal memory register of the VR controller; and where the method further comprises:

using the at least one processing device as a VR controller to:

receive the power device identification signal output from the at least one IPstage,

determine the identity of the at least one IPstage based on the received power device identification signal,

retrieve information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage from the internal memory register of the VR controller, and

provide the indicated FET drive voltage control signal value to the power stage gate drive VR; and

using the power stage gate drive VR to provide a regulated gate drive voltage based on the value of the retrieved FET drive voltage control signal provided by the VR controller to drive a gate of the FET switching devices of the at least one IPstage while using the VR controller to control the at least one IPstage to provide power to the VR system voltage output.

10. The method of claim 9 , where the FET switching devices comprise MOSFET switching devices.

11. A method of operating a voltage regulator (VR) system using at least one processing device, comprising:

using the at least one processing device to control operation of at least one integrated power stage (IPstage) to provide regulated power to a voltage output of the VR system, the at least one IPstage also including a voltage input, and one or more field effect transistor (FED switching devices coupled between the voltage input and the voltage output;

using the at least one processing device to:

receive a power device identification signal output from the at least one IPstage that is indicative of the identity of the at least one IPstage;

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

provide the FET drive voltage control signal to a power stage gate drive VR;

where the memory accessible by the VR controller also stores information indicative of FET drive voltage control signal values for different types of IPstages, each of the multiple different types of IPstages has different drain to source resistance in on-state characteristics as a function of gate drive voltage or gate-to-source voltage.

12. A method of operating a voltage regulator (VR) system using at least one processing device, comprising:

using the at least one processing device to:

receive a power device identification signal output from the at least one IPstage that is indicative of the identity of the at least one IPstage,

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

provide the FET drive voltage control signal to a power stage gate drive VR;

using the at least one processing device as a VR controller to receive and store the power device identification signal output from the at least one IPstage in an internal memory register of the VR controller;

using at least one separate external processing device to:

retrieve the stored IPstage power device identification signal output from the internal memory register of the VR system controller,

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

provide the determined FET drive voltage control signal value to the power stage gate drive VR; and

using the power stage gate drive VR to provide a determined regulated FET drive voltage based on the determined FET drive voltage control signal value to drive the FET switching devices of the at least one IPstage while using the at least one processing device to control the at least one IPstage to provide power to the voltage output.

13. The method of claim 12 , where the at least one external processing device is a service processor or a host CPU processing device executing system basic input/output system (BIOS).

14. An information handling system, comprising:

at least one processing device configured as a voltage regulator (VR) system controller that is coupled to control operation of the at least one IPstage, the VR controller also being coupled to receive the power device identification signal output from the at least one IPstage;

a power stage gate drive VR coupled between the VR controller and the at least one IPstage, the power stage gate drive VR being configured to provide a regulated gate drive voltage to drive the FET switching devices of the at least one IPstage; and

at least one processing device configured to:

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

memory accessible by the VR system controller having information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage stored thereon together with information indicative of FET drive voltage control signal values for different types of IPstages;

where the memory further comprises at least one of non-volatile memory coupled to the VR controller or an internal memory register provided within the VR controller, at least one of the NVM or the internal memory register storing information indicative of PET drive voltage control signal values corresponding to multiple different types of IPstages that include the at least one IPstage; and where the VR controller is further configured to:

determine the identity of the at least one IPstage based on the received power device identification signal,

retrieve information indicative of a FET drive voltage control signal value that corresponds to the identified IPstage from the NVM or internal memory register, and

provide the indicated FET drive voltage control signal value to the power stage gate drive VR; and

15. An information handling system, comprising:

at least one integrated power stage (IPstage) comprising a voltage input, a voltage output one or more field effect transistor (FET) switching devices coupled between the voltage input and the voltage output to provide regulated power to the voltage output, and an IPstage identification (ID) recognition module having a power device identification signal output that is indicative of the identity of the at least one IPstage;

at least one processing device configured to:

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

where each of the different types of IPstages have different drain to source resistance in on-state characteristics as a function of gate drive voltage or gate-to-source voltage; and where the VR system controller is configured to identify and retrieve the information indicative of a FET drive voltage control signal value that corresponds to the identified type of IPstage from the memory.

16. An information handling system, comprising:

at least one processing device configured to:

determine a FET drive voltage control signal value based at least in part on the received power device identification signal, and

at least one processing device that is separate and external to the VR system controller; where the VR system controller comprises an internal memory register configured to receive and store the power device identification signal output from the at least one IPstage; where each of the VR system controller and the power stage gate drive VR are coupled to the at least one separate external processing device; and where the at least one external processing device is configured to:

retrieve the stored IPstage power device identification signal output from the internal memory register of the VR system controller,

determine a FET drive voltage control signal value based at least in part on the retrieved power device identification signal, and

17. The information handling system of claim 16 , where the at least one external processing device is service processor or a host CPU processing device executing system basic input/output system (BIOS).

Assignments (15)

RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022

From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT

To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC

Reel/Frame 071642/0001 →

RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (045455/0001) Recorded May 20, 2022

From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT

To: DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO ASAP SOFTWARE EXPRESS, INC.); DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC CORPORATION (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MAGINATICS LLC); EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); SCALEIO LLC

Reel/Frame 061753/0001 →

RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (040136/0001) Recorded Apr 26, 2022

From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT

Reel/Frame 061324/0001 →

RELEASE OF SECURITY INTEREST Recorded Nov 3, 2021

From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH

To: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL, L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; WYSE TECHNOLOGY L.L.C.

Reel/Frame 058216/0001 →

SECURITY AGREEMENT Recorded Apr 22, 2020

From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC

To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.

Reel/Frame 053546/0001 →

SECURITY AGREEMENT Recorded Mar 21, 2019

From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC

To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.

Reel/Frame 049452/0223 →

SECURITY AGREEMENT Recorded Sep 21, 2016

From: ASAP SOFTWARE EXPRESS, INC.; AVENTAIL LLC; CREDANT TECHNOLOGIES, INC.; DELL USA L.P.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL SOFTWARE INC.; DELL SYSTEMS CORPORATION; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; FORCE10 NETWORKS, INC.; MAGINATICS LLC; MOZY, INC.; SCALEIO LLC; SPANNING CLOUD APPS LLC; WYSE TECHNOLOGY L.L.C.

To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT

Reel/Frame 040134/0001 →

SECURITY AGREEMENT Recorded Sep 21, 2016

To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT

Reel/Frame 040136/0001 →

RELEASE OF REEL 034590 FRAME 0731 (NOTE) Recorded Sep 14, 2016

From: BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT

To: DELL PRODUCTS L.P.

Reel/Frame 040027/0070 →

RELEASE OF REEL 034591 FRAME 0391 (TL) Recorded Sep 14, 2016

From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT

To: DELL PRODUCTS L.P.