Systems and Methods for Rank Deficient Encoding

1 . A data processing system, the system comprising:

an encoder circuit operable to:

receive a user data input;

matrix multiply the user data input by a first quasi-cyclic parity component to yield a first interim value;

matrix multiply the first interim value by an inverse left factor Smith Normal component to yield a second interim value;

matrix multiply the second interim value by a pseudo inverse diagonal factor Smith Normal component to yield a third interim value;

matrix multiply the third interim value by an inverse right factor Smith Normal component to yield a first parity portion;

matrix multiply the first parity portion by a second quasi-cyclic parity component to yield a fourth interim value; and

vector add the first interim value to the fourth interim value to yield a second parity portion.

2 . The data processing system of claim 1 , wherein the encoder circuit is further operable to:

assemble at least the user data input, the first parity portion, and the second parity portion into an encoded codeword.

3 . The data processing system of claim 1 , wherein the encoder circuit is further operable to:

matrix multiply the user data input by a third quasi-cyclic parity component to yield a third parity portion.

4 . The data processing system of claim 3 , wherein the encoder circuit is further operable to:

assemble the user data input, the first parity portion, the second parity portion and the third parity portion into an encoded codeword.

5 . The data processing system of claim 3 , wherein the encoder circuit includes a memory operable to store the first quasi-cyclic parity component, the inverse left factor Smith Normal component, the pseudo inverse diagonal factor Smith Normal component, the inverse left factor Smith Normal component, and the second quasi-cyclic parity component.

6 . The data processing system of claim 5 , wherein the encoder circuit includes:

a first matrix multiplier circuit operable to matrix multiply the user data input by the first quasi-cyclic parity component to yield the first interim value;

a second matrix multiplier circuit operable to matrix multiply the first interim value by the inverse left factor Smith Normal component to yield the second interim value;

a third matrix multiplier circuit operable to matrix multiply the second interim value by the pseudo inverse diagonal factor Smith Normal component to yield the third interim value;

a fourth matrix multiplier circuit operable to matrix multiply the third interim value by the inverse right factor Smith Normal component to yield the first parity portion;

a fifth matrix multiplier circuit operable to matrix multiply the first parity portion by a second quasi-cyclic parity component to yield a fourth interim value;

a vector addition circuit operable to vector add the first interim value to the fourth interim value to yield the second parity portion; and

a sixth matrix multiplier circuit operable to matrix multiply the user data input by the third quasi-cyclic parity component to yield the third parity portion.

7 . The data processing system of claim 6 , wherein each of the first matrix multiplier circuit, the second matrix multiplier circuit, the fourth matrix multiplier circuit, the fifth matrix multiplier circuit, and the sixth matrix multiplier circuit are configured to multiply an input by a quasi-cyclic matrix.

8 . The data processing system of claim 6 , wherein third matrix multiplier circuit is configured to multiply an input by a non-quasi-cyclic matrix.

9 . The data processing system of claim 1 , wherein the pseudo inverse diagonal factor Smith Normal component is a non-quasi-cyclic component.

10 . The data processing system of claim 9 , wherein both the inverse right factor Smith Normal component and the inverse left factor Smith Normal component are quasi-cyclic components.

11 . The data processing system of claim 1 , wherein the data processing system is implemented as part of a device selected from a group consisting of: a storage device, and a communication device.

12 . The data processing system of claim 1 , wherein the data processing system is implemented as part of an integrated circuit.

13 . A method for data encoding, the method comprising:

calculating components for a rank deficient encoder, wherein the component calculation includes applying a Smith Normal conversion to an input matrix that yields left factor Smith Normal component, a diagonal factor Smith Normal conversion, and a right factor Smith Normal component;

inverting the left factor Smith Normal component to yield an inverse left factor Smith Normal component, wherein the inverse left factor Smith Normal component is a quasi-cyclic matrix;

inverting the diagonal factor Smith Normal component to yield a pseudo inverse diagonal factor Smith Normal component, wherein the pseudo inverse diagonal factor Smith Normal component is a non-quasi-cyclic matrix;

inverting the right factor Smith Normal component to yield an inverse left factor Smith Normal component, wherein the inverse left factor Smith Normal component is a quasi-cyclic matrix; and

storing the inverse left factor Smith Normal component, the pseudo inverse diagonal factor Smith Normal component, and the inverse right factor Smith Normal component to a memory device.

14 . The method of claim 13 , the method further comprising:

receiving a user data input;

matrix multiplying the user data input by a first quasi-cyclic parity component to yield a first interim value;

matrix multiplying the first interim value by the inverse left factor Smith Normal component to yield a second interim value;

matrix multiplying the second interim value by the pseudo inverse diagonal factor Smith Normal component to yield a third interim value;

matrix multiplying the third interim value by the inverse right factor Smith Normal component to yield a first parity portion;

matrix multiplying the first parity portion by a second quasi-cyclic parity component to yield a fourth interim value; and

vector adding the first interim value to the fourth interim value to yield a second parity portion.

15 . The method of claim 14 , wherein the method further comprises:

matrix multiplying the user data input by a third quasi-cyclic parity component to yield a third parity portion.

16 . The method of claim 14 , wherein the method further comprises:

assembling the user data input, the first parity portion, the second parity portion and the third parity portion into an encoded codeword.

17 . The method of claim 14 , wherein each of the matrix multiplying the user data input by the first quasi-cyclic parity component to yield the first interim value, matrix multiplying the first interim value by the inverse left factor Smith Normal component to yield the second interim value, matrix multiplying the third interim value by the inverse right factor Smith Normal component to yield the first parity portion, and matrix multiplying the first parity portion by the second quasi-cyclic parity component to yield the fourth interim value are done using respective matrix multiplier circuits configured to multiply an input by a quasi-cyclic matrix.

18 . The method of claim 14 , wherein matrix multiplying the second interim value by the pseudo inverse diagonal factor Smith Normal component to yield the third interim value is done using a matrix multiplier circuit configured to multiply an input by a non-quasi-cyclic matrix.

19 . The method of claim 14 , wherein the method further comprises:

transferring the encoded codeword to a destination selected from a group consisting of: a storage medium, and a receiver.

20 . A data storage device, the device comprising:

a storage medium;

a head disposed in relation to the storage medium and operable to write an encoded data set to the storage medium;

an encoder circuit operable to:

receive a user data input;

matrix multiply the user data input by a first quasi-cyclic parity component to yield a first parity portion;

matrix multiply the user data input by a second quasi-cyclic parity component to yield a first interim value;

matrix multiply the first interim value by an inverse left factor Smith Normal component to yield a second interim value;

matrix multiply the second interim value by a pseudo inverse diagonal factor Smith Normal component to yield a third interim value;

matrix multiply the third interim value by an inverse right factor Smith Normal component to yield a third parity portion;

matrix multiply the third parity portion by a third quasi-cyclic parity component to yield a fourth interim value;

vector add the first interim value to the fourth interim value to yield a second parity portion; and

assemble the user data input, the first parity portion, the second parity portion and the third parity portion into an encoded codeword, wherein the encoded data set is derived from the encoded codeword.