Devices and methods for converting digital signals
View Patent ↗A signal converter directly converts pulse-density-modulated (PDM) signals into pulse-width-modulated (PWM) signals. A noise-shaping loop architecture can be configured to apply a signal transfer function having a low-pass filter effect, and a noise transfer function having a high-pass filter effect. Decimation and interpolation can ensure that the noise-shaping loop architecture operates at a first sampling frequency, while the PWM modulator operates at a second, higher sampling frequency.
1. A signal converter, comprising:
an input configured to receive a pulse-density-modulated (PDM) signal at a first sampling frequency;
an output for outputting a pulse-width-modulated (PWM) signal at a second sampling frequency;
an add/subtract unit for producing a difference signal by subtracting a feedback signal from the PDM signal;
a loop filter for filtering the difference signal to produce a filtered signal;
an interpolation filter for generating an interpolated signal by interpolating the filtered signal from the first sampling frequency to the second sampling frequency;
a modulator for generating the PWM signal based on the interpolated signal and a carrier signal; and
a decimation filter for producing the feedback signal as a decimated representation of the PWM signal.
2. The signal converter according to claim 1 , wherein a signal transfer function of the signal converter has a low-pass filter effect.
3. The signal converter according to claim 1 , wherein a noise-transfer function of the signal converter has a high-pass effect.
4. The signal converter according to claim 1 , wherein the
second sampling frequency is greater than the first sampling frequency.
5. The signal converter according to claim 1 , wherein the interpolation filter comprises a sample-and-hold device.
6. The signal converter according to claim 5 , wherein the sample-and-hold device is clocked at the first sampling frequency.
7. The signal converter according to claim 5 , further comprising logic circuitry coupled to the interpolation filter and the decimation filter, configured to determine whether the interpolated signal and the carrier signal will intersect in a next clock period of the sample-and-hold device, and to control the decimation filter to output a value based on said determination.
8. The signal converter according to claim 7 , wherein the logic circuitry is further configured to determine, if the interpolated signal and the carrier signal intersect in the next clock period of the sample-and-hold device, a phase of the intersection of the interpolated signal with the carrier signal, and to control the decimation filter to output a value based on said determined phase.
9. The signal converter according to claim 8 , wherein the phase of the intersection is expressed as an integer number of clock periods at the second sampling frequency.
10. The signal converter according to claim 8 , wherein the decimation filter comprises a look-up table storing one or more step responses.
11. The signal converter according to claim 8 , wherein the decimation filter is clocked at the first sampling frequency.
12. The signal converter according to claim 1 , wherein the decimation filter comprises a low-pass filter and a sampler.
13. The signal converter according to claim 1 , wherein the decimation filter comprises a look-up table with a plurality of stored step responses.
14. The signal converter according to claim 1 , wherein the carrier signal has a third frequency which is lower than the first sampling frequency.
15. The signal converter according to claim 1 , wherein the modulator comprises a comparator for comparing the interpolated signal with the carrier signal and supplying a signal indicative of the comparison as the PWM signal.
16. The signal converter according to claim 1 , wherein the PWM signal is a binary signal.
17. The signal converter according to claim 1 , wherein the carrier signal is a sawtooth signal or a triangle-wave signal.
18. A method of generating a pulse-width-modulated (PWM) signal at a second sampling frequency from a pulse-density-modulated (PDM) signal at a first sampling frequency, the method comprising:
subtracting a feedback signal from the PDM signal to produce a difference signal;
filtering the difference signal to produce a filtered signal;
interpolating the filtered signal from the first sampling frequency to the second sampling frequency;
generating the PWM signal based on the interpolated signal and a carrier signal; and
producing the feedback signal as a decimated representation of the PWM signal.
19. The method according to claim 18 , wherein the method applies a signal transfer function having a low-pass filter effect.
20. The method according to claim 18 , wherein the method applies a noise-transfer function having a high-pass filter effect.
21. The method according to claim 18 ,
wherein the second sampling frequency is greater than the first sampling frequency.