Method and system for a low input voltage low impedance termination stage for current inputs

1. A semiconductor device, the device comprising:

an output stage for an electrical circuit, the output stage comprising a pair of input cascode transistors and at least one pair of stacked output transistors, wherein a source-follower feedback path for the input cascode transistors comprises a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors, a drain of the feedback transistor coupled to a supply voltage, and a source terminal of the feedback transistor coupled to a current source that is coupled to ground.

2. The semiconductor device according to claim 1 , wherein a current source is coupled to the drain of the first of the input cascode transistors.

3. The semiconductor device according to claim 1 , wherein the supply voltage is coupled to the at least one pair of stacked output transistors via a load resistor.

4. The semiconductor device according to claim 1 , wherein the input cascode transistors, the feedback transistor, and the at least one pair of stacked output transistors comprise complementary metal-oxide semiconductor (CMOS) transistors.

5. The semiconductor device according to claim 1 , wherein a current through the input cascode transistors is controlled by a bias voltage applied to a gate terminal of the first of the input cascode transistors.

6. The semiconductor device according to claim 1 , wherein the electrical circuit comprises a power amplifier.

7. The semiconductor device according to claim 6 , wherein the power amplifier comprises a differential gain stage coupled to a source terminal of the first of the cascode transistors and a drain of a second of the cascode transistors.

8. The semiconductor device according to claim 1 , wherein the electrical circuit comprises a digital-to-analog converter (DAC).

9. The semiconductor device according to claim 8 , wherein the DAC comprises a plurality of unit cells, each cell coupled to a source terminal of the first of the cascode transistors and a drain of a second of the cascode transistors.

10. The semiconductor device according to claim 9 , wherein each of the plurality of unit cells are also coupled to cascode transistors in a second output stage nominally identical to the output stage.

11. The semiconductor device according to claim 1 , wherein a feedback circuit comprising a resistor and capacitor in series is coupled from the pair of input cascode transistors to a load resistance that is coupled to the at least one pair of stacked output transistors.

12. A method for communication, the method comprising:

in a semiconductor die, generating an output current that is proportion to an input signal, said output current generated by an output stage, the output stage comprising:

a pair of input cascode transistors and at least one pair of stacked output transistors; and

a source-follower feedback path for the input cascode transistors, said source-follower feedback path comprising:

a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors;

a drain of the feedback transistor coupled to a supply voltage;

and a source terminal of the feedback transistor coupled to a current source that is coupled to ground.

13. The method according to claim 12 , wherein a current source is coupled to the drain of the first of the input cascode transistors.

14. The method according to claim 12 , wherein the supply voltage is coupled to the at least one pair of stacked output transistors via a load resistor.

15. The method according to claim 12 , wherein the input cascode transistors, the feedback transistor, and the at least one pair of stacked output transistors comprise complementary metal-oxide semiconductor (CMOS) transistors.

16. The method according to claim 12 , comprising controlling a current through the input cascode transistors with a bias voltage applied to a gate terminal of the first of the input cascode transistors.

17. The method according to claim 12 , wherein the electrical circuit comprises a power amplifier.

18. The method according to claim 17 , wherein the power amplifier comprises a differential gain stage coupled to a source terminal of the first of the cascode transistors and a drain of a second of the cascode transistors.

19. The method according to claim 12 , wherein the electrical circuit comprises a digital-to-analog converter (DAC).

20. The method according to claim 19 , wherein the DAC comprises a plurality of unit cells, each cell coupled to a source terminal of the first of the cascode transistors and a drain of a second of the cascode transistors and wherein each of the plurality of unit cells are also coupled to cascode transistors in a second output stage nominally identical to the output stage.

21. The method according to claim 12 , wherein a feedback circuit comprising a resistor and capacitor in series is coupled from the pair of input cascode transistors to a load resistance that is coupled to the at least one pair of stacked output transistors.

22. A semiconductor device comprising:

a pair of output stages for a digital-to-analog converter (DAC), the output stages each comprising:

a pair of input cascode transistors;

at least one pair of stacked output transistors;

a feedback path comprising a resistor and capacitor in series coupled from the pair of input cascode transistors to a load resistance that is coupled to the at least one pair of stacked output transistors; and

a source-follower feedback path for the input cascode transistors, said source-follower feedback path comprising:

a feedback transistor with its gate terminal coupled to a drain terminal of a first of the input cascode transistors;

a drain of the feedback transistor coupled to a supply voltage;

and a source terminal of the feedback transistor coupled to a current source that is coupled to ground.