IP Library Granted Patent US 9,425,337
Granted Patent B2
US 9,425,337 · App. 14/472,232 · Granted Aug 23, 2016

In-cell bypass diode

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,425,337
App. No.
14/472,232
Granted
Aug 23, 2016
Kind
B2
Abstract

A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.

Claims (11)

1. A method of fabricating a bypass diode for a solar cell, the method comprising:

providing a semiconductor substrate having a first conductivity;

forming a first P-N junction above a first portion of the semiconductor substrate;

forming a metallization structure on at least a portion of the first P-N junction and on at least a portion of a second P-N junction disposed in or above a second portion of the semiconductor substrate so as to couple the first P-N junction to the second P-N junction above a first surface of the semiconductor substrate; and

subsequently physically isolating the first portion of the semiconductor substrate from the second portion so as to form an in-cell bypass diode from the second portion, wherein the isolating includes forming a trench in the semiconductor substrate through a surface of the semiconductor substrate opposite the first surface which includes the first junction P-N and the second P-N junction.

2. The method of claim 1 , wherein said physically isolating includes scribing the semiconductor substrate in a first direction and a second direction.

3. The method of claim 1 , wherein said physically isolating includes scribing with a laser.

4. The method of claim 1 , wherein said forming the first P-N junction above the first portion includes forming abutting P-type and N-type polysilicon regions.

5. The method of claim 1 , further comprising forming the second P-N junction in or above the second portion of the semiconductor substrate is part of a same one or more processing operations used to perform said forming the first P-N junction.

6. The method of claim 1 , wherein said forming the metallization structure includes plating and patterning metal.

7. The method of claim 1 , further comprising dicing the solar cell to form two sub-cells each having a respective bypass diode that comprises a portion of the first P-N junction.

Assignments (5)
SECURITY INTEREST Recorded Jun 27, 2024
From: MAXEON SOLAR PTE. LTD.
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 067924/0062 →
SECOND LIEN SECURITY INTEREST AGREEMENT Recorded Jun 26, 2024
From: MAXEON SOLAR PTE. LTD
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 071343/0553 →
SECURITY INTEREST Recorded Jun 5, 2024
From: MAXEON SOLAR PTE. LTD.
To: DB TRUSTEES (HONG KONG) LIMITED
Reel/Frame 067637/0598 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 24, 2023
From: SUNPOWER CORPORATION
To: MAXEON SOLAR PTE. LTD.
Reel/Frame 062699/0875 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 6, 2015
From: RIM, SEUNG BUM; HARLEY, GABRIEL
To: SUNPOWER CORPORATION
Reel/Frame 035574/0393 →