High voltage fail-safe IO design using thin oxide devices
View Patent ↗A high-voltage fail-safe input/output (I/O) interface circuit includes a voltage-divider circuit coupled to an I/O pad of the I/O interface circuit, and a selector circuit configured to couple, to a power supply line of the I/O interface circuit one of an output of the voltage-divider circuit or and I/O supply voltage. The voltage-divider circuit and the selector circuit are implemented on the same chip with the I/O interface circuit.
1. An input/output (I/O) interface circuit, the circuit comprising:
a voltage-divider circuit coupled to an I/O pad of the I/O interface circuit; and
a selector circuit comprising a multiplexer configured to select one of an output of the voltage-divider circuit or an I/O supply voltage based on a fail-safe detection signal, wherein:
the voltage-divider circuit and the selector circuit are implemented on the same chip as the I/O interface circuit.
2. The circuit of claim 1 , wherein the supply voltage comprises a high supply voltage and is used to generate a lower supply voltage, wherein the lower supply voltage is larger than a core supply voltage.
3. The circuit of claim 1 , further comprising a fail-safe detection logic circuit, wherein the fail-safe detection logic circuit is configured to generate the fail-safe detection signal based on the I/O supply voltage not being available.
4. The circuit of claim 1 , wherein the voltage-divider circuit is configured to generate a voltage that is a percentage of a magnitude of an input signal coupled to the I/O pad.
5. The circuit of claim 1 , further comprising an internal clamp circuit configured to clamp the I/O supply voltage to a low voltage to prevent voltage overstresses on the I/O interface circuit during a fail-safe mode of operation.
6. The circuit of claim 5 , wherein the internal clamp circuit is configured to clamp the I/O supply voltage to a lower voltage based on a fail-safe detection signal.
7. The circuit of claim 6 , wherein the fail-safe detection signal is generated based on the I/O supply voltage not being available.
8. The circuit of claim 5 , wherein the internal clamp circuit comprises a switch controllable by the fail-safe detection signal.
9. The circuit of claim 1 , wherein the voltage-divider circuit includes one or more switches that are configurable to disable the voltage-divider circuit based on a fail-safe detection signal, wherein the fail-safe detection signal is generated based on the I/O supply voltage not being available.
10. A method for providing an input/output (I/O) interface circuit, the method comprising:
providing a voltage-divider circuit and a selector circuit comprising a multiplexer on a same chip with the I/O interface circuit;
coupling the voltage-divider circuit to an I/O pad of the I/O interface circuit; and
configuring the multiplexer to select one of an output of the voltage-divider circuit or an I/O supply voltage based on a fail-safe detection signal.
11. The method of claim 10 , wherein the I/O supply voltage comprises a high supply voltage, wherein the method comprises using the high supply voltage to generate a lower supply voltage, and wherein the lower supply voltage is larger than a core supply voltage.
12. The method of claim 10 , further comprising configuring a fail-safe detection logic circuit to generate the fail-safe detection signal based on the I/O supply voltage not being available.
13. The method of claim 10 , further comprising configuring the voltage-divider circuit to generate a voltage that is a percentage of a magnitude of an input signal coupled to the I/O pad.
14. The method of claim 10 , further comprising configuring an internal clamp circuit to prevent overvoltage stresses on the I/O interface circuit during a fail-safe mode of operation by clamping the I/O supply voltage to a low voltage.
15. The method of claim 14 , wherein configuring the internal clamp circuit to prevent voltage overstresses on the I/O interface circuit during the fail-safe mode of operation comprises clamping the I/O supply voltage to a lower voltage based on a fail-safe detection signal.
16. The method of claim 14 , further comprising providing the internal clamp circuit by using a switch controllable by the fail-safe detection signal and generating the fail-safe detection signal based on the I/O supply voltage not being available.
17. The method of claim 10 , wherein providing the voltage-divider comprises providing one or more switches.
18. The circuit of claim 10 , further comprising configuring the one or more switches to disable the divider circuit based on a fail-safe detection signal and generating the fail-safe detection signal based on the I/O supply voltage not being available.
19. A chip comprising:
one or more I/O pads;
one or more I/O interface circuits, each of the one or more I/O interface circuits coupled to at least one of the one or more I/O pads and comprising:
a voltage-divider circuit coupled to a corresponding I/O pad of the respective I/O interface circuit; and
a selector circuit comprising a multiplexer configured to select one of an output of the voltage-divider circuit or an I/O supply voltage based on a fail-safe detection signal.
20. The chip of claim 19 , wherein:
the I/O supply voltage comprises a high supply voltage and is used to generate a lower supply voltage, wherein the lower supply voltage is larger than a core supply voltage, and
the voltage-divider circuit includes one or more switches that are configurable to disable the voltage-divider circuit based on a fail-safe detection signal, wherein the fail-safe detection signal is generated based on the I/O supply voltage not being available.