System and method for simulating a memory technology

1. An information handling system for simulating a memory channel, the information handling system comprising:

a memory for storing code; and

a processor operative to execute code to:

model a design of a memory channel to provide a plurality of transfer functions associated with the design, wherein a particular one of the transfer functions models a memory configuration on the memory channel;

perform a Fast Fourier Transform (FFT) on an input bitstream to the memory channel to provide an input spectrum;

multiply the input spectrum with each of the transfer functions to provide a plurality of results;

sum the results to provide an output spectrum for the design;

perform an inverse FFT on the output spectrum to provide an output signal for the design;

generate an eye diagram from the output signal; and

determine a bit error rate (BER) for the design based on the eye diagram.

2. The information handling system of claim 1 , wherein the plurality of transfer functions comprise a forward memory channel transfer function, a memory channel cross-talk transfer function, a voltage regulator transfer function, a power plane resonance transfer function, and a broadside coupling transfer function.

3. The information handling system of claim 2 , wherein the processor is further configured to:

receive the forward memory channel transfer function, the memory channel cross-talk transfer function, the voltage regulator transfer function, the power plane resonance transfer function, and the broadside coupling transfer function from a circuit simulation of the design.

4. The information handling system of claim 1 , wherein the processor is further configured to:

determine that the design meets a specification based upon the BER.

5. The information handling system of claim 1 , wherein the input bitstream comprises greater than one million bits.

6. The information handling system of claim 1 , wherein the input bitstream comprises a random sequence of bits.

7. The information handling system of claim 1 , wherein the input bitstream comprises a sequence of bits associated with a worst case condition for the memory channel.

8. A method for simulating a memory channel, the method comprising:

modeling a design of a memory channel to provide a plurality of transfer functions associated with the design, wherein a particular one of the transfer functions models a memory configuration on the memory channel;

performing a Fast Fourier Transform (FFT) on an input bitstream to the memory channel to provide an input spectrum;

multiplying the input spectrum with each of the transfer functions to provide a plurality of results;

summing the results to provide an output spectrum for the design;

performing an inverse FFT on the output spectrum to provide an output signal for the design;

generating an eye diagram from the output signal; and

determining a bit error rate (BER) for the design based on the eye diagram.

9. The method of claim 8 , wherein the plurality of transfer functions comprise a forward memory channel transfer function, a memory channel cross-talk transfer function, a voltage regulator transfer function, a power plane resonance transfer function, and a broadside coupling transfer function.

10. The method of claim 9 , further comprising:

receiving the forward memory channel transfer function, the memory channel cross-talk transfer function, the voltage regulator transfer function, the power plane resonance transfer function, and the broadside coupling transfer function from a circuit simulation of the design.

11. The method of claim 8 , further comprising:

determining that the design meets a specification based upon the BER.

12. The method of claim 8 , wherein the input bitstream comprises greater than one million bits.

13. The method of claim 8 , wherein the input bitstream comprises a random sequence of bits.

14. The method of claim 8 , wherein the input bitstream comprises a sequence of bits associated with a worst case condition for the memory channel.