Nonvolatile semiconductor memory device

1. A nonvolatile semiconductor memory device comprising:

first and second word line groups, each including a plurality of stacked word lines above a substrate having first and second layers that are insulated from each other;

a first memory string including a first memory column through the first word line group, a second memory column through the second word line group, and a first memory connection portion electrically coupling the first and second memory columns; and

a second memory string including a third memory column through the first word line group, a fourth memory column through the second word line group, and a second memory connection portion electrically coupling the third and fourth memory columns, wherein

the first memory connection portion is formed in the first layer of the substrate and the second memory connection portion is formed in the second layer of the substrate that is lower than the first layer.

2. The device according to claim 1 , wherein the first and second memory connection portions extend in a first direction that is perpendicular to a second direction along which each of the stacked word lines extend, and the first memory connection portion is bounded by the second memory connection portion in the first direction and is aligned with a part of the second memory connection portion in the second direction.

3. The device according to claim 1 , wherein the stacked word lines of the first and second word line groups extend in a first direction, and the first and second memory connection portions each extend in a second direction that is transverse to the first direction, to connect the first and second memory columns, and the third and fourth memory columns, respectively.

4. The device according to claim 3 , wherein the first and third memory columns are aligned partially in the first direction and no portions of the first and third memory columns are aligned in the second direction, and the second and fourth memory columns are aligned partially in the first direction and no portions of the second and fourth memory columns are aligned in the second direction.

5. The device according to claim 1 , wherein the first and third memory columns are linearly symmetrical to the second and fourth memory columns with respect to a straight line which connects a middle point of a first line segment connecting the first and second memory columns to a middle point of a second line segment connecting the third and fourth memory columns.

6. The device according to claim 1 , wherein the first layer comprise a back gate for the first memory string driven by a first back gate driving circuit and the second layer comprise a back gate for the second memory string driven by a second back gate driving circuit, and the first and second layers are separated by an insulating layer.

7. The device according to claim 1 , further comprising:

first and second selection gates, which are selection gates for the first and second memory strings, formed respectively over the first and second word line groups; and

third and fourth selection gates, which are selection gates for the third and fourth memory strings formed respectively over the second and third word line groups,

wherein the second selection gate is electrically connected to the third selection gate.

8. The device according to claim 1 , further comprising:

first and second selection gates, which are selection gates for the first and second memory strings, formed respectively over the first and second word line groups; and

third and fourth selection gates, which are selection gates for the third and fourth memory strings formed respectively over the second and third word line groups,

wherein the second selection gate is electrically insulated from the third selection gate.

9. The device according to claim 8 , further comprising:

a third memory string including a fifth memory column through the first word line group, a sixth memory column through the second word line group, and a third memory connection portion electrically connecting the fifth and sixth memory columns, wherein

the substrate has a third layer that is lower than and insulated from the first and second layers, and

the third memory connection portion is formed in the third layer of the substrate.

10. The device according to claim 9 , wherein

the first, second, and third memory connection portions extend in a first direction that is perpendicular to a second direction along which each of the stacked word lines extend, and

the first memory connection portion is bounded by the second memory connection portion in the first direction and is aligned with a part of the second memory connection portion in the second direction, and the second connection portion is bounded by the third memory connection portion in the first direction and is aligned with a part of the third memory connection portion in the second direction.

11. A nonvolatile semiconductor memory device comprising:

first and second word line groups, each of which includes a plurality of stacked word lines that extend in a first direction;

a first memory column through the first word line group and electrically connected to a first bit line;

a second memory column through the second word line group and electrically connected to a second bit line, the second memory column being disposed at a same position as the first memory column in the first direction;

a third memory column through the first word line group, adjacent to the first memory column in a second direction perpendicular to the first direction, and disposed at a position deviated from the first memory column in the first direction;

a fourth memory column through the second word line group, and disposed at a same position as the third memory column in the first direction; and

a memory connection portion that electrically connects the first to fourth memory columns to each other,

wherein, when a memory cell of the first memory column is selected, the first bit line is connected to a sense amplifier, and a source line voltage is supplied to the second bit line, and

wherein, when a memory cell of the second memory column is selected, the second bit line is connected to the sense amplifier, and the source line voltage is supplied to the first bit line.

12. The device according to claim 11 , wherein

when data is read from a memory cell of the second memory column, the second bit line is connected to the sense amplifier, and the source line voltage is supplied to the first bit line, and

when data is to be written to memory cells of the first memory column and the second memory column, the first bit line and the second bit line are connected to the sense amplifier, and a voltage corresponding to the data to be written is applied from the sense amplifier to the first bit line and the second bit line.