METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Extension regions 7 are formed through implantation using offset sidewalls 6 a of a footing profile as a mask, and sidewalls 9 are formed on the offset sidewalls 6 a so that source and drain regions 10 are formed into the sidewall through implantation, so that the extension regions 7 are made separated away from both edges of the gate, contributing to enlargement in an effective gate length, and dealing with the narrowed gate pitch, without increasing the number of processes.
1 . A method of manufacturing a semiconductor device comprising:
forming a gate electrode on a semiconductor substrate of a first conductive type;
forming a first insulating film on the semiconductor substrate and the gate electrode;
etching the first insulating film to form first sidewall spacers on both sides of the gate electrode;
doping second conductive type impurities on a surface of the semiconductor substrate, using the first sidewall spacers as a mask;
forming a second insulating film on the semiconductor substrate and the first sidewall spacers;
etching the second insulating film to form second sidewall spacers on the first sidewall spacers; and
doping second conductive type impurities on the surface of the semiconductor substrate using the second sidewall spacers as a mask,
wherein each of the first sidewall spacers has a footing portion including a slope, and wherein an angle between a tangent line at a point of the slope and the surface of the semiconductor substrate becomes gradually small when the point becomes closer to the surface of the semiconductor substrate, and
wherein the first sidewall spacers are formed by terminating the etching of the first insulating film when the layer under the first sidewall spacer is exposed.
2 . The method of claim 1 , wherein a portion of the first sidewall spacers is substantially parallel with a side of the gate electrode.
3 . The method of claim 2 , wherein a width L2 between a lower edge of the gate electrode and a lower end of the footing portion is approximately twice of a width L1 of the first sidewall spacer at the position where the first sidewall spacer is parallel with a side of the gate electrode.
4 . The method of claim 1 , wherein the second sidewall spacers completely cover the first sidewall spacers.
5 . The method of claim 4 , wherein the second sidewall spacers do not have a footing portion including a slope.
6 . The method of claim 1 , further comprising doping first conductive type impurities on the surface of the semiconductor substrate using the first sidewall spacers as a mask, after doping the second conductive type impurities with the low concentration on the surface of the semiconductor substrate using the first sidewall spacers as a mask.
7 . The method of claim 1 , wherein the gate electrode comprises a metal material.
8 . The method of claim 1 , wherein the gate electrode has the gate length of not more than 150 nm.