Embedded instrumentation architecture
The various technologies presented herein relate to generating copies of an incoming signal, wherein each copy of the signal can undergo different processing to facilitate control of bandwidth demands during communication of one or more signals relating to the incoming signal. A signal sharing component can be utilized to share copies of the incoming signal between a plurality of circuits/components which can include a first A/D converter, a second A/D converter, and a comparator component. The first A/D converter can operate at a low sampling rate and accordingly generates, and continuously transmits, a signal having a low bandwidth requirement. The second A/D converter can operate at a high sampling rate and hence generates a signal having a high bandwidth requirement. Transmission of a signal from the second A/D converter can be controlled by a signaling event (e.g., a signal pulse) being determined to have occurred by the comparator component.
1. An integrated circuit comprising:
a first analog to digital (A/D) converter;
a second A/D converter; and
a signal sharing component, the signal sharing component comprising:
an input pin;
a first output pin communicatively coupled to the first A/D converter; and
a second output pin communicatively coupled to the second A/D converter, wherein the signal sharing component:
receives a process signal on the input pin; and
directs the process signal to each of the first output pin and the second output pin, such that a first sample of the process signal is received by the first A/D converter and a second sample of the process signal is received by the second A/D converter, the first A/D converter processes the first sample of the process signal at a first sampling rate to form a first converted signal, the second A/D converter processes the second sample of the process signal at a second sampling rate to form a second converted signal, and the first sampling rate is lower than the second sampling rate.
2. The integrated circuit of claim 1 , wherein the signal sharing component is a demultiplexor.
3. The integrated circuit of claim 1 , wherein the process signal is an analog signal.
4. The integrated circuit of claim 1 , wherein the first A/D converter further comprises a third output pin, and the second A/D converter further comprises a fourth output pin.
5. The integrated circuit of claim 4 , further comprising a comparator that comprises a fifth output pin, the comparator is configured to receive the process signal, perform a comparison between a magnitude of the process signal and a threshold value, and output a signal based upon the comparison.
6. The integrated circuit of claim 5 , wherein the first A/D converter transmits the first converted signal on the third output pin when the signal output by the comparator indicates that the magnitude of the process signal received at the comparator is below the threshold value.
7. The integrated circuit of claim 6 , further comprising a memory buffer, the second A/D converter transmits the second converted signal to the memory buffer over the fourth output pin when the signal output by the comparator indicates that the magnitude of the process signal received at the comparator is below the threshold value.
8. The integrated circuit of claim 5 , wherein the second A/D converter transmits the second converted signal on the fourth output pin when the signal output by the comparator indicates that the magnitude of the process signal received at the comparator is equal to, or above, the threshold value.
9. The integrated circuit of claim 5 , further comprising a configuration component, the configuration component facilitates programming of the comparator with a threshold value setting, wherein the threshold value setting is utilized to configure the threshold value.
10. The integrated circuit of claim 1 , wherein the integrated circuit is incorporated into an application-specific integrated circuit (ASIC).
11. A method comprising:
receiving a process signal on an input channel of a signal sharing component;
concurrently forming a first replication of the process signal, a second replication of the process signal, and a third replication of the process signal;
transmitting the first replication of the process signal to a first analog to digital (A/D) converter, wherein the first A/D converter:
converts the first replication of the process signal to a first digital signal; and
transmits the first digital signal on a first communication bus;
transmitting the second replication of the process signal to a second A/D converter, wherein the second A/D converter converts the second replication of the process signal to a second digital signal wherein the first A/D converter is configured to convert the first replication of the process signal to the first digital signal at a sampling rate that is less than the sampling rate utilized by the second A/D converter to convert the second replication of the process signal to the second digital signal; and
transmitting the third replication of the process signal to a comparator, wherein the comparator compares a magnitude of the third replication of the process signal to a threshold value and in response to determining that the magnitude of the third replication of the process signal is greater than the threshold value, the comparator transmits a first notification that causes the second digital signal to be output on the communication bus.
12. The method of claim 11 , wherein the signal sharing component, the first A/D converter, the second A/D converter, and the comparator are incorporated into an application-specific integrated circuit (ASIC).
13. The method of claim 11 , further comprising receiving at the comparator a threshold value setting, and in response to receiving the threshold value setting, updating the threshold value to equal the threshold value setting.
14. The method of claim 11 , wherein, in response to receiving the first notification at a controller, the controller initiates transmission of the second digital signal at the second A/D converter, the transmission is to the communication bus.
15. The method of claim 11 , further comprising:
at the comparator:
determining that the magnitude of the third replication of the process signal is less than the threshold value; and
in response to determining the magnitude of the third replication of the process signal is less than the threshold value, transmitting a second notification to the controller.
16. The method of claim 15 , further comprising:
causing the second digital signal to be discarded at the second A/D converter.
17. A method comprising:
receiving a process signal on an input channel of a signal sharing component;
forming a first replication of the process signal and a second replication of the process signal;
transmitting the first replication of the process signal to a first analog to digital (A/D) converter;
at the first A/D converter and at a first sampling rate, converting the first replication of the process signal to a first sample signal and transmitting the first sample signal on a communication bus; and
transmitting the second replication of the process signal to a second A/D converter;
at the second A/D converter and at a second sampling rate that is higher than the first sampling rate, converting the second replication of the process signal to a second sample signal
storing the second sample signal in a memory buffer;
receiving the process signal at a comparator, wherein the process signal is received at the comparator concurrent with the process signal being received at the signal sharing component, wherein the comparator compares a magnitude of the process signal to a threshold value and in response to determining the magnitude of the process signal is greater than the threshold value, the comparator transmits a notification that causes the second sample signal to be output on the communication bus.