Calibration of a time-interleaved analog-to-digital converter (ADC) circuit

1. An apparatus for calibration of an analog-to-digital converter (ADC) including a plurality of sub-ADCs comprising:

a reference sub-ADC among the plurality of sub-ADCs;

a calibration-signal generator configured to provide a calibration signal at an input node of each sub-ADC of the plurality of sub-ADCs; and

a gain-correction path configured to generate, for each sub-ADC of the plurality of sub-ADCs, other than the reference sub-ADC, a corresponding error signal based on output signals of the sub-ADC and the reference sub-ADC, wherein

each sub-ADC is configured to be calibrated based on the corresponding error signal,

the ADC comprises a time-interleaved ADC that includes the plurality of sub-ADCs, and

the reference sub-ADC is configured to have a lowest relative offset among the plurality of sub-ADCs.

2. The apparatus of claim 1 , wherein:

the apparatus is configured to allow the reference sub-ADC to be selected from the plurality of sub-ADCs based on measuring an offset of each sub-ADC,

when the ADC comprises a single-ended ADC, selecting the reference sub-ADC from the plurality of sub-ADCs comprises measuring an offset of each sub-ADC of the plurality of sub-ADCs while the input node of that sub-ADC is shorted to ground potential,

when the ADC comprises a differential ADC, selecting the reference sub-ADC from the plurality of sub-ADCs comprises measuring an offset of each sub-ADC of the plurality of sub-ADCs while shorting to each other positive and negative inputs of the sub-ADC,

the relative offset comprises an offset of the sub-ADC relative to a specified target offset value, and

a value of the relative offset is an absolute value of the difference between the offset the sub-ADC and the specified target offset value.

3. The apparatus of claim 2 , wherein the gain-correction path is configured to act to reduce a mean-square difference between the output signals of that sub-ADC and the reference sub-ADC.

4. The apparatus of claim 1 , further comprising an offset-correction path configured to generate, for each sub-ADC, a corresponding offset-error signal based on the corresponding error signal,

wherein:

the offset-correction path comprises a first accumulator and is configured to generate the corresponding offset-error signal based on using a first software-controlled parameter and the first accumulator,

the offset-correction path is configured to calibrate each sub-ADC based on the corresponding error signal by adjusting an offset of each sub-ADC at an output node of that sub-ADC in digital domain, and

the offset-correction path is configured to adjust the offset of each sub-ADC at the output node of that sub-ADC by generating a new value for the output signal of the sub-ADC by combining the corresponding offset-error signal with a previous value of the output signal of the sub-ADC.

5. The apparatus of claim 4 , further comprising an offset error monitor configured to automatically detect a convergence of the offset-correction path, by:

allowing the offset-calibration loop to run for N-WAIT cycles before starting to check if the offset-calibration loop has converged, wherein N-WAIT is programmable, wherein N-WAIT comprises an integer greater than zero;

determining that the convergence of the offset-calibration loop is reached when an absolute offset-correction and a cycle-to-cycle change in offset-correction are within predetermined tolerances; and

when the convergence of the offset-calibration loop is not reached, allowing the offset-calibration loop to run for up to a maximum N-MAX-ITER more cycles until the convergence of the offset-calibration loop is reached or non-convergence is detected as a BIST failure, wherein N-MAX-ITER is programmable, wherein N-MAX-ITER comprises an integer greater than zero.

6. The apparatus of claim 1 , wherein:

the gain-correction path is configured to calibrate each sub-ADC based on the corresponding error signal by adjusting a corresponding reference voltage of each sub-ADC,

the gain-correction path is configured to adjust the corresponding reference voltage of each sub-ADC by modifying an input digital code to a corresponding gain-adjustment digital-to-analog converter (DAC) that generates the reference voltage of each sub-ADC,

the gain-correction path is configured to modify the input digital code to the corresponding gain-adjustment DAC based on the corresponding gain-error signal,

the gain-correction path is configured to generate the corresponding gain-error signal by using a product of three terms comprising the corresponding error signal, a sign of the output signal of the reference sub-ADC, and a software-controlled parameter, and accumulating the product in a second accumulator, and

the apparatus further comprises:

gain-correction registers configured to store a corresponding gain-correction including the modified input digital code to gain-adjustment DACs for later retrieval, and

a gain error monitor configured to automatically detect a convergence of the gain-correction path.

7. The apparatus of claim 6 , wherein the gain error monitor is configured to:

allow the gain-correction path to run for N-WAIT cycles before starting to check if the gain-calibration loop has converged, wherein N-WAIT is programmable, wherein N-WAIT comprises an integer greater than zero;

determine that the convergence of the gain-calibration loop is reached when an absolute gain-correction and a cycle-to-cycle change in gain-correction are within predetermined tolerances; and

when the convergence of the gain-calibration loop is not reached, allow the gain-calibration loop to run for up to a maximum N-MAX-ITER more cycles until the convergence of the gain-calibration loop is reached or non-convergence is detected as a BIST failure, wherein N-MAX-ITER is programmable, wherein N-MAX-ITER comprises an integer greater than zero.

8. The apparatus of claim 7 , the gain-error monitor is further configured to detect functionality faults of the ADC by:

applying the corresponding error signal, the corresponding offset-error signal, and the corresponding gain-error signal to a built-in self-test (BIST) circuit;

performing a startup calibration;

receiving failure reports from the BIST circuit, when the gain-correction path or the offset-correction path fails to converge or a gross ADC mismatch is detected by the BIST circuit.

9. The apparatus of claim 8 , wherein the gain error monitor is configured to perform the startup calibration after an initialization of a chip or following a cold start of the chip, and wherein the BIST circuit is configured to report the gross ADC mismatch when the corresponding error signal is larger than a predetermined fail-threshold provided to the BIST circuit.

10. The apparatus of claim 8 , wherein the functionality faults include nonlinearity, critical random errors, and electronic over-stress (EOS) faults, and wherein the gain-error monitor is configured to detect the functionality faults of the ADC without adversely affecting functionalities of the ADC.

11. The apparatus of claim 1 , further comprising an ADC-to-ADC calibration module configured to:

determine that an offset-correction path and a gain-correction path of the ADC are converged; and

in response to the determination that offset-correction path and a gain-correction path of the ADC are converged, use a value of the relative offset associated with the reference sub-ADC as an offset value for another ADC, wherein each of the ADC and the other ADC are implemented by time-interleaving a plurality of sub-ADCs.

12. The apparatus of claim 1 , wherein the calibration-signal generator is configured to generate the calibration signal that comprises:

distinct values,

a square wave with added white Gaussian Noise, and

an adjustable amplitude.

13. The apparatus of claim 1 , wherein the gain-correction path is configured to determine an amplitude for the calibration signal by:

applying the calibration signal with an initial amplitude value to the reference sub-ADC, wherein the initial amplitude value comprises a highest value; and

successively decrementing in a loop the possible subsequent amplitude values of the calibration signal to reach the amplitude for the calibration signal, for which the output signal of the reference sub-ADC is no longer clipped.

14. The apparatus of claim 1 , further comprising a startup calibration module and a background calibration module, wherein:

the startup calibration module is configured to perform a startup calibration after an initialization of a chip or following a cold start of the chip,

the background calibration module is configured to perform the background calibration after the startup calibration and during normal operation of the chip, subsequent to a warm start following an idle state, or in response to an external return command,

the startup calibration and the background calibration are bypass-able by external commands, and

the idle state is reached after a freeze resulting from an external freeze command or a loss of signal.

15. An apparatus for correction of a timing impairment of a time-interleaved analog-to-digital converter (ADC), comprising:

an interleaver circuit coupled to a plurality of sub-ADCs of the ADC and configured to receive clock signals and generate a plurality of current signals;

a plurality of integrators configured to convert the plurality of current signals to a plurality of voltage signals that are applied to the plurality of sub-ADCs; and

a gain-correction path configured to correct the timing impairment of the ADC based on using a calibration signal to adjust gains associated with the plurality of sub-ADCs,

wherein:

the timing impairment of the ADC is based on timing distortion associated with the clock signal and results in gain mismatch between the plurality of sub-ADCs, and

adjusting gains associated with the plurality of sub-ADCs compensates for gain mismatches between the plurality of sub-ADCs.

16. The apparatus of claim 15 , wherein the gain correction path is configured to adjust gains associated with the plurality of sub-ADCs by using different gain adjustments for the even sub-ADCs and odd sub-ADCs, and wherein the gain-correction path is configured to adjust gains associated with the plurality of sub-ADCs by:

selecting a reference sub-ADC from the plurality of sub-ADCs;

sending a calibration signal to an input node of each sub-ADC of the plurality of sub-ADCs; and

for each sub-ADC of the plurality of sub-ADCs, other than the reference sub-ADC, generating a corresponding error signal based on output signals of the sub-ADC and the reference sub-ADC, and

wherein:

the gain-correction path is configured to calibrate each sub-ADC based on the corresponding error signal, and

the reference sub-ADC has a lowest relative offset among the plurality of sub-ADCs.

17. The apparatus of claim 16 , wherein:

the gain-correction path is configured to select the reference sub-ADC from the plurality of sub-ADCs by measuring the offset of each sub-ADC of the plurality of sub-ADCs,

when the ADC comprises a single-ended ADC, the gain-correction path is configured to select the reference sub-ADC from the plurality of sub-ADCs by measuring an offset of each sub-ADC of the plurality of sub-ADCs while the input node of that sub-ADC is shorted to ground potential,

when the ADC comprises a differential ADC, the gain-correction path is configured to select the reference sub-ADC from the plurality of sub-ADCs by measuring an offset of each sub-ADC of the plurality of sub-ADCs while shorting to each other positive and negative inputs of the sub-ADC,

the relative offset comprises an offset of the sub-ADC relative to a specified target offset value, and

a value of the relative offset comprises an absolute value of a difference between the offset of the sub-ADC and the specified target offset value.

18. The apparatus of claim 17 , wherein the gain-correction path is configured to act to reduce a mean-square difference between the output signals of that sub-ADC and the reference sub-ADC.

19. The apparatus of claim 16 , wherein the gain-correction path is configured to:

generate, for each sub-ADC, a corresponding gain-error signal based on the corresponding error signal;

calibrate each sub-ADC based on the corresponding error signal by adjusting a corresponding reference voltage of each sub-ADC;

adjust the corresponding reference voltage of each sub-ADC by modifying an input digital code to a corresponding gain-adjustment digital-to-analog converter (DAC) that generates the reference voltage of each sub-ADC;

modify the input digital code to the corresponding gain-adjustment DAC based on the corresponding gain-error signal;

generate the corresponding gain-error signal by using a product of three terms comprising the corresponding error signal, a sign of the output signal of the reference sub-ADC, and a software-controlled parameter and then accumulating the product in a second accumulator; and

store a corresponding gain-correction including the modified input digital code to gain-adjustment DACs for later retrieval, and

wherein the apparatus further comprises a gain error monitor configured to automatically detect a convergence of the gain-correction path.

20. An apparatus for correction of a timing impairment of a time-interleaved analog-to-digital converter (ADC), comprising:

an interleaver circuit coupled to a plurality of odd and even sub-ADCs of the ADC and configured to receive clock signals and generate a plurality of current signals;

a plurality of integrators configured to convert the plurality of current signals to a plurality of voltage signals that are applied to the plurality of sub-ADCs; and

a comparator configured to determine timing impairment of the ADC based on a comparison between an average gain of the odd sub-ADCs with an average gain of the even sub-ADCs,

wherein:

the timing impairment of the ADC is based on timing distortions associated with the clock signals, and results in gain mismatch between the even sub-ADCs and odd sub-ADCs, and

the timing impairment of the ADC is correctable based on adjusting timings associated with the clock signals.