Ferroelectric memory device and timing circuit to control the boost level of a word line

1. A semiconductor memory device, comprising:

a memory cell array configured to include a plurality of memory cells;

a word line decoder configured to control selection and a voltage level of a word line connected to each of the memory cells;

a time determination signal generation circuit configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined; and

a timing circuit configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged,

wherein the control of whether or not a selected word line is pre-charged is carried out when, after a write command is output, the write command to write first data is output by setting a potential of a bit line connected to the memory cell to a power supply voltage and setting a potential of a plate line connected to the memory cell to a ground potential, and

wherein the control of whether or not a selected word line is pre-charged is carried out when the first data is written after second data that are different from the first data have been written to all of the memory cells.

2. The semiconductor memory device according to claim 1 , wherein the time determination signal generation circuit is installed in the timing circuit.

3. The semiconductor memory device according to claim 1 , wherein the control signal controls a decoder circuit in the word line decoder.

4. The semiconductor memory device according to claim 1 , wherein the change in a command corresponds to a cycle time with which the memory cell is accessed.

5. The semiconductor memory device according to claim 1 , wherein the semiconductor memory device further comprises a column line decoder configured to control selection of a bit line connected to each of the memory cells.

6. The semiconductor memory device according to claim 5 , wherein:

the semiconductor memory device is a ferroelectric memory, and

the semiconductor memory device further comprises a plate line decoder configured to control selection of a plate line connected to each of the memory cells.

7. The semiconductor memory device according to claim 6 , wherein the memory cells each comprise a 1T1C-type ferroelectric memory cell which contains a transistor and a capacitor.

8. The semiconductor memory device according to claim 1 , wherein the command is a chip enable signal.

9. A semiconductor memory device, comprising:

a memory cell array configured to include a plurality of memory cells;

a word line decoder configured to control selection and a voltage level of a word line connected to each of the memory cells;

a time determination signal generation circuit configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined; and

a timing circuit configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged, wherein the timing circuit compares a chip enable signal with the time determination signal and pre-charges the selected word line when an enable time by the chip enable signal is longer than the determination time by the time determination signal.

10. A semiconductor memory device, comprising:

a memory cell array configured to include a plurality of memory cells;

a word line decoder configured to control selection and a voltage level of a word line connected to each of the memory cells;

a time determination signal generation circuit configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined; and

a timing circuit configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged, wherein the time determination signal generation circuit further comprises a word line decoder monitoring circuit configured to monitor a leakage current in the word line decoder, and generate the time determination signal by using an output signal of the word line decoder monitoring circuit.

11. A semiconductor memory device, comprising:

a memory cell array configured to include a plurality of memory cells;

a word line decoder configured to control selection and a voltage level of a word line connected to each of the memory cells;

a time determination signal generation circuit configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined; and

a timing circuit configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged, wherein the time determination signal generation circuit further comprises a differential amplifier configured to define the determination time in the time determination signal by comparing a gate voltage of a transfer gate transistor connected to the word line with a reference voltage, the word line being monitored by the word line decoder monitoring circuit.

12. The semiconductor memory device according to claim 11 , wherein a potential of the reference voltage is configured to be adjustable.

13. The semiconductor memory device according to claim 1 , wherein the word line decoder is configured to boost a gate voltage of a transfer gate transistor connected to the selected word line in a plurality of steps.