DC-DC converter having terminals of semiconductor chips directly attachable to circuit board
A power supply system ( 200 ) has a QFN leadframe with leads and a pad ( 201 ). The pad surface facing a circuit board has a portion recessed with a depth ( 270 ) and an outline suitable for attaching side-by-side the sync ( 210 ) and the control ( 220 ) FET semiconductor chips. The input terminal ( 220 a ) of the control FET and the grounded output terminal ( 210 a ) of the sync FET are coplanar with the un-recessed portion of the pad (switch node terminal) so that all terminals can be directly attached to contacts of a circuit board. A driver-and-control chip ( 230 ) is vertically stacked to the opposite pad surface and encapsulated in a packaging compound ( 290 ).
1. A method for fabricating a power supply system comprising:
providing a leadframe having leads and a pad with a first and a second surface, the first surface having a portion recessed with a depth and an outline suitable for attaching semiconductor chips;
attaching a driver-and-control chip on the second surface of the pad;
connecting the terminals of the driver-and-control chip to respective leads using bonding wires;
encapsulating the driver-and-control chip, the bonding wires, and the second pad surface in a packaging compound, while leaving the first pad surface un-encapsulated;
then attaching a first field-effect transistor (FET) chip with its drain terminal to the recessed portion of the first pad surface so that the source and gate terminals of the first FET chip are co-planar with the un-recessed portion of the first pad surface; and
attaching a second FET chip with its source terminal to the recessed portion of the first pad surface so that the drain and gate terminals of the second FET chip are co-planar with the un-recessed portion of the first pad surface.
2. The method of claim 1 further including the processes of connecting the pad to the switch node terminal of the system, the source terminal of the first FET chip to a board terminal as a grounded output terminal of the system, and the drain of the second FET chip to a board terminal as an input terminal of the system.
3. The method of claim 1 wherein the processes of attaching employ attach material selected from a group including conductive adhesives and polymeric compounds with z-axis conductor.
4. The method of claim 1 wherein the leadframe has the configuration of a Quad Flat No-Lead (QFN) or Small Outline No-Lead (SON) type.