IP Library Granted Patent US 9,627,391
Granted Patent B2
US 9,627,391 · App. 14/483,259 · Granted Apr 18, 2017

Non-volatile memory device

Inventor: Hiroki Yamashita (Yokkaichi, JP)
Assignee: Kabushiki Kaisha Toshiba
H01L27/11519H01L27/1157H01L27/11524H01L27/11556H01L27/11565H01L27/11582
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Quick Facts
Patent No.
US 9,627,391
App. No.
14/483,259
Granted
Apr 18, 2017
Kind
B2
Abstract

According to one embodiment, a non-volatile memory device includes electrodes, an interlayer insulating film, at least one semiconductor layer, conductive layers, first and second insulating films. The electrodes are arranged in a first direction. The interlayer insulating film is provided between the electrodes. The semiconductor layer extends in the first direction in the electrodes and the interlayer insulating film. The conductive layers are provided between each of the electrodes and the semiconductor layer, and separated from each other in the first direction. The first insulating film is provided between the conductive layers and the semiconductor layer. The second insulating film is provided between each of the electrodes and the conductive layers, and extends between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes. A width of the conductive layers in the first direction is narrower than that of the second insulating film.

Claims (44)

1. A non-volatile memory device, comprising:

a plurality of memory cells stacked in a first direction and electrically connected in series, at least one of the memory cells including:

a control gate electrode;

a first channel extending in the first direction through the control gate electrode;

a conductive layer provided between the control gate electrode and the first channel;

a first insulating film provided between the conductive layer and the first channel; and

a second insulating film provided between the control gate electrode and the conductive layer,

a width of the conductive layer in the first direction being narrower than a width of the second insulating film in the first direction,

the conductive layer having a first side surface on the first channel side and a second side surface on the control gate electrode side, and

a length of the first side surface in the first direction being longer than a length of the second side surface in the first direction; and

a selection transistor provided above the memory cells, the selection transistor including:

a selection gate electrode; and

a second channel extending in the first direction and connected on one end of the first channel.

2. The device according to claim 1 , wherein the conductive layer includes at least one of a conductive film containing silicon, a metal film, and a conductive film containing a metal oxide.

3. The device according to claim 1 , wherein the conductive layer has a stacked structure including a third insulating film and at least one of a conductive film containing silicon, a metal film, and a conductive film containing a metal oxide.

4. The device according to claim 1 , wherein

the control gate electrode and an interlayer insulating film are alternately arranged in the first direction,

the first channel is provided inside a first hole piercing the control gate electrode and the interlayer insulating film alternately arranged, and

the first insulating film extends in the first direction along the first channel.

5. The device according to claim 1 , wherein the second insulating film includes an oxide containing at least one element selected from silicon, zirconium, hafnium, tantalum, lanthanum, and aluminum.

6. The device according to claim 1 , wherein the second insulating film includes an oxynitride containing at least one element selected from silicon, zirconium, hafnium, tantalum, lanthanum, and aluminum.

7. The device according to claim 1 , wherein the second insulating film has a stacked structure including an oxide containing at least one element selected from silicon, zirconium, hafnium, tantalum, lanthanum, and aluminum and an oxynitride containing at least one element selected from silicon, zirconium, hafnium, tantalum, lanthanum, and aluminum.

8. A non-volatile memory device, comprising:

electrodes arranged in a first direction;

at least one semiconductor layer extending in the first direction through the electrodes;

conductors each provided between each of the electrodes and the semiconductor layer, a length of the conductors in the first direction being shorter than a length of the electrodes in the first direction;

a first insulating film provided between the conductors and the semiconductor layer; and

a second insulating film provided between each of the electrodes and the conductors,

wherein the conductors have a size less than 3 nm, and include ones of at least two or more different sizes.

9. The device according to claim 8 , wherein the conductors are one of silicon, a metal, and a metal oxide.

10. The device according to claim 9 , wherein the first insulating film covers the conductors.

11. The device according to claim 10 , further comprising:

an interlayer insulating film provided between the electrodes, and

the first insulating film having a first portion between the conductors and the semiconductor layer and a second portion between the interlayer insulating film and the semiconductor layer, wherein

a thickness of the first portion in a direction perpendicular to the first direction is larger than a thickness of the second portion in the first direction.

12. The device according to claim 8 , further comprising:

an interlayer insulating film provided between the electrodes, and

the second insulating film extending between each of the electrodes and the interlayer insulating film adjacent to the each of the electrodes.

13. The device according to claim 1 , wherein a gate insulating film is provided between the selection gate electrode and the second channel, the conductive layer being not provided between the selection gate electrode and the second channels.

14. The device according to claim 4 , wherein

the second channel is provided inside a second hole piercing the selection gate electrode, and

a dimension of the second hole is different from that of the first hole in a direction perpendicular to the first direction.

15. The device according to claim 1 , wherein a width of the selection gate electrode in the first direction is larger than a width of the control gate electrode in the first direction.

16. The device according to claim 1 , wherein a position of the second channel is shifted from that of the first channel in a direction perpendicular to the first direction.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043355/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2014
From: YAMASHITA, HIROKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 034199/0296 →
Continuity (2)
Provisional Application 62023031 · Jul 10, 2014
Related Publication 20160013200A1 · Jan 14, 2016