IP Library Granted Patent US 9,519,534
Granted Patent B2
US 9,519,534 · App. 14/483,346 · Granted Dec 13, 2016

Information processing in response to failure of apparatus, method, and storage medium

Inventor: Masatoshi Sugino (Chiba, JP)
Assignee: FUJITSU LIMITED
G06F11/0778G06F11/0721G06F11/0787
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Quick Facts
Patent No.
US 9,519,534
App. No.
14/483,346
Granted
Dec 13, 2016
Kind
B2
Abstract

An information processing apparatus includes a processor, a first memory, and a second memory, wherein the second memory includes a first data storage region having a first data capacity and a second data storage region having a second data capacity smaller than the first data capacity, and the processor is configured to, in a case of executing first processing, select the first data storage region as a storage region for data to be written into the second memory by the first processing, and select the second data storage region as a storage region for data to be written into the second memory by second processing, and in a case of not executing the first processing, select the first data storage region as a storage region for data to be written from the first memory to the second memory by the second processing.

Claims (42)

1. An information processing apparatus, comprising:

a processor configured to perform data processing;

a first memory coupled to the processor and configured to store processing data obtained by the data processing performed by the processor; and

a second memory coupled to the processor,

wherein a first data storage region is set in the second memory and a second data storage region not overlapping with the first data storage region is set in the second memory, the second data storage region having a second data capacity and the first data storage region having a first data capacity smaller than the second data capacity, and

the processor is configured to,

when the information processing apparatus operates normally, select the second data storage region as a storage region for data to be written from the first memory to the second memory by swap processing, and select the first data storage region as a storage region for data to be written from the first memory to the second memory by dump processing, and

when a failure occurs in the information processing apparatus, select the second data storage region as the storage region for data to be written from the first memory to the second memory by the dump processing.

2. The information processing apparatus according to claim 1 , wherein

a third data storage region is set in the second memory, the third data storage region being configured to store region data indicating the storage region for the processing data to be written from the first memory to the second memory in the swap processing, and,

the processor is configured to, when a failure occurs in the information processing apparatus, write first region data indicating the first storage region as the region data in the third data storage region, and

when the information processing apparatus operates normally, write second region data indicating the second data storage region as the region data in the third data storage region.

3. The information processing apparatus according to claim 2 , wherein

a flag region is set in the second memory, the flag region being configured to store a flag indicating a content of the region data stored in the third data storage region, and

the processor is configured to rewrite the region data based on the flag stored in the flag region.

4. The information processing apparatus according to claim 1 , wherein the second data capacity is larger than a capacity of the first memory.

5. The information processing apparatus according to claim 1 , wherein

the first memory is a volatile memory, and

the second memory is a non-volatile memory.

6. The information processing apparatus, according to claim 1 , wherein the first data capacity is smaller than a capacity of the first memory.

7. An information processing method using an information processing apparatus including a processor, a first memory, and a second memory, the information processing method comprising:

setting a first data storage region and a second data region not overlapping with the first data storage region in the second memory, the second data storage region having a second data capacity and the first data storage region having a first data capacity smaller than the second data capacity;

performing data processing using the processor and storing processing data in the first memory;

when the information processing apparatus operates normally, selecting the second data storage region as a storage region for data to be written from the first memory to the second memory by swap processing, and selecting the first data storage region as a storage region for data to be written from the first memory to the second memory by dump processing; and

when a failure occurs in the information processing apparatus, selecting the second data storage region as the storage region for data to be written from the first memory to the second memory by the dump processing.

8. The information processing method according to claim 7 , the method further comprising:

setting a third data storage region in the second memory, the third data storage region being configured to store region data indicating the storage region for the processing data to be written from the first memory to the second memory in the swap processing;

when a failure occurs in the information processing apparatus, writing first region data indicating the first storage region as the region data in the third data storage region; and

when the information processing apparatus operates normally, writing second region data indicating the second data storage region as the region data in the third data storage region.

9. The information processing method according to claim 8 , the method further comprising:

setting a flag region in the second memory, the flag region being configured to store a flag indicating a content of the region data stored in the third data storage region; and

rewriting the region data based on the flag stored in the flag region.

10. The information processing method according to claim 7 , wherein the second data capacity is larger than a capacity of the first memory.

11. The information processing method according to claim 7 , wherein

the first memory is a volatile memory, and

the second memory is a non-volatile memory.

12. The information processing method according to claim 7 , wherein the first data capacity is smaller than a capacity of the first memory.

13. A non-transitory computer-readable storage medium storing a program that causes an information processing apparatus to execute a process, the information processing apparatus including a processor, a first memory, and a second memory, the process comprising:

setting a first data storage region and a second data storage region not overlapping with the first data storage region in the second memory, the second data storage region having a second data capacity and the first data storage region having a first data capacity smaller than the second data capacity;

performing data processing by using the processor and storing processing data in the first memory;

when the information processing apparatus operates normally, selecting the second data storage region as a storage region for data to be written from the first memory to the second memory by swap processing, and selecting the first data storage region as a storage region for data to be written from the first memory to the second memory by dump processing; and

when a failure occurs in the information processing apparatus, selecting the second data storage region as the storage region for data to be written from the first memory to the second memory by the dump processing.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ORIGINAL COVER SHEET BY REMOVING PATENT NUMBER 10586039 PREVIOUSLY RECORDED ON REEL 69272 FRAME 546. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 1, 2025
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 070764/0091 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2024
From: FUJITSU LIMITED
To: FSAS TECHNOLOGIES INC.
Reel/Frame 069272/0546 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2014
From: SUGINO, MASATOSHI
To: FUJITSU LIMITED
Reel/Frame 033727/0549 →
Priority Claims (1)
JP 2013-251848 · Dec 5, 2013 · national
Continuity (1)
Related Publication 20150161032A1 · Jun 11, 2015