IP Library Granted Patent US 9,153,488
Granted Patent B1
US 9,153,488 · App. 14/483,561 · Granted Oct 6, 2015

Semiconductor device, resistor and manufacturing method of the same

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,153,488
App. No.
14/483,561
Granted
Oct 6, 2015
Kind
B1
Abstract

A resistor includes a first conductive layer; a second conductive layer protruding from the first conductive layer; a third conductive layer located above and facing the first conductive layer to face the first conductive layer; and at least two contact plugs electrically coupled to the third conductive layer.

Claims (18)

1. A method for manufacturing a semiconductor device, the method comprising:

forming a first conductive layer including a first trench;

forming a sacrificial layer in the first trench;

forming a second conductive layer on the first conductive layer where the sacrificial layer is formed;

forming a second trench exposing the sacrificial layer by patterning the first and second conductive layers, wherein the first conductive layer is patterned into a plate shape and the second conductive layer is patterned into a plurality of lines;

removing the sacrificial layer through the second trench; and

forming an insulating layer in the first and second trenches,

wherein during the forming of the first conductive layer, another conductive layer for a pipe gate made of a same material as the first conductive layer is formed in a cell region, wherein the conductive layer for the pipe gate includes a third trench, and

wherein during the forming of the second trench, a fourth trench is formed in the conductive layer for the pipe gate to pattern the conductive layer into pipe gates in the cell region.

2. The method according to claim 1 ,

wherein the first conductive layer is located in a resistor region.

3. The method according to claim 1 ,

further comprising:

forming a plurality of contact plugs electrically coupled to the plurality of lines.

4. The method according to claim 1 ,

wherein the forming the second trench uses the sacrificial layer as an etching barrier.

5. The method according to claim 1 ,

wherein during the forming of an insulating layer, forming an isolation layer made of a same material as the insulating layer in the fourth trench.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2014
From: EOM, DAE SUNG
To: SK HYNIX INC.
Reel/Frame 033721/0575 →