Bottom gate TFT with multilayer passivation
View Patent ↗A transistor includes a gate in contact with a substrate. A gate insulating layer is in contact with at least the gate. An inorganic semiconductor layer is in contact with the gate insulating layer. There is a source electrode in contact with a first portion of the inorganic semiconductor layer and a drain electrode in contact with a second portion of the inorganic semiconductor layer, and the source electrode and the drain electrode are separated by a gap. There is a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap. The multilayer structure includes an inorganic dielectric layer having a first pattern defining a first area; and a polymer structure having a second pattern defining a second area. The second area is located within the first area and the polymer structure is in contact with the semiconductor layer in the gap.
1. A transistor comprising:
a substrate;
a gate in contact with the substrate;
a gate insulating layer in contact with at least the gate;
an inorganic semiconductor layer in contact with the gate insulating layer;
a source electrode in contact with a first portion of the inorganic semiconductor layer;
a drain electrode in contact with a second portion of the inorganic semiconductor layer, the source electrode and the drain electrode separated by a gap; and
a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap, the multilayer structure including:
an inorganic dielectric layer having a first pattern defining a first area; and
a multilayer polymer structure comprising:
a first polymeric layer having a second pattern defining second area located within the first area; and
a second polymeric layer in contact with the first polymeric layer and with the semiconductor layer in the gap, the second polymeric layer having a third pattern defining a third area located within the second area, wherein the third area is smaller than the second area.
2. The transistor of claim 1 , wherein the first polymeric layer is not in contact with the semiconductor layer in the gap.
3. The transistor of claim 1 , further comprising another inorganic dielectric layer that is conformal and extends beyond the first area.
4. The transistor of claim 1 , wherein the first area is equal to the second area.
5. The transistor of claim 1 , wherein the multilayer insulating structure is in contact with a portion of the source electrode and a portion of the drain electrode.
6. The transistor of claim 1 , wherein the transistor is an enhancement mode device.
7. The transistor of claim 1 , wherein the inorganic semiconductor is a metal oxide semiconductor.
8. The transistor of claim 7 , wherein the metal oxide semiconductor is a ZnO based semiconductor.
9. The transistor of claim 1 , the gate being a first gate, further comprising:
a second gate located on the multilayer insulating structure on a side of the multilayer insulating structure opposite the first gate, and over at least a portion of the gap.
10. The transistor of claim 9 , wherein the first gate and the second gate are aligned relative to each other.
11. The transistor of claim 9 , wherein the first gate and the second gate overlap each other in the gap.
12. A transistor comprising:
a substrate;
a gate in contact with the substrate;
a gate insulating layer in contact with at least the gate;
an inorganic semiconductor layer in contact with the gate insulating layer;
a source electrode in contact with a first portion of the inorganic semiconductor layer;
a drain electrode in contact with a second portion of the inorganic semiconductor layer, the source electrode and the drain electrode separated by a gap; and
a multilayer insulating structure in contact with at least the inorganic semiconductor layer in the gap, the multilayer structure including:
an inorganic dielectric layer having a first pattern defining a first area; and
a multilayer polymer structure comprising:
a first polymeric layer having a second pattern defining second area located within the first area; and
a second polymeric layer in contact with the first polymeric layer and with the semiconductor layer in the gap, the second polymeric layer having a third pattern defining a third area located within the second area, wherein the first area extends beyond the second area to define a reentrant profile under the inorganic dielectric layer, the transistor further comprising another inorganic dielectric layer that is conformal and extends beyond the first area.