Semiconductor device
A semiconductor device according to an aspect of the invention relates to an AD converter that converts a signal level of an analog signal into a digital value by using a comparator, and determines an amount of adjustment of an offset voltage of the comparator based on an offset determination result of the comparator obtained immediately after a least significant bit (LSB) of a digital value output as a conversion result is converted.
1. A semiconductor device comprising:
a sample-and-hold circuit that samples a voltage level of an input voltage according to a sampling clock signal, outputs one of differential voltages corresponding to the voltage level of the input voltage to a first comparison line, and outputs the other of the differential voltages to a second comparison line;
a comparator that outputs an output value indicating a high level or a low level according to a voltage difference between the first comparison line and the second comparison line;
a digital-to-analog conversion circuit that changes voltages of the first comparison line and the second comparison line according to the output value;
a successive approximation control circuit that controls the sample-and-hold circuit, the comparator, and the digital-to-analog conversion circuit according to a preset successive approximation sequence, and outputs a number of output values corresponding to the number of bits of a conversion result output value; and
a switch circuit that is provided between the first comparison line and the second comparison line, a conductive state and a cut-off state of the switch circuit being switched by the successive approximation control circuit, wherein
upon acquisition of the output value of all bits of the conversion result output value, the successive approximation control circuit brings the switch circuit into the conductive state, and outputs an offset determination signal for adjusting an input offset voltage of the comparator according to the output value during a period in which the switch circuit is in the conductive state, and
the comparator changes the input offset voltage according to an offset control value generated according to a logic level of the offset determination signal.
2. The semiconductor device according to claim 1 , further comprising an offset control circuit that increases or decreases the offset control value according to the logic level of the offset determination signal output from the successive approximation control circuit, wherein
the comparator includes:
a pre-amplifier that amplifies the voltage difference between the first comparison line and the second comparison line, and outputs a first intermediate output voltage and a second intermediate output voltage;
a latch circuit that determines a logic level of the output value according to a voltage difference between the first intermediate output voltage and the second intermediate output voltage;
a first offset adjustment capacitor connected to a first intermediate voltage line through which the first intermediate output voltage is transmitted; and
a second offset adjustment capacitor connected to a second intermediate voltage line through which the second intermediate output voltage is transmitted,
a capacitance ratio between the first offset adjustment capacitor and the second offset adjustment capacitor being changed according to the offset control value.
3. The semiconductor device according to claim 2 , wherein
when the logic level of the offset determination signal is a first logic level, the offset control circuit increases the offset control value, and
when the logic level of the offset determination signal is a second logic level, the offset control circuit decreases the offset control value.
4. The semiconductor device according to claim 2 , wherein the offset control circuit updates the offset control value in each conversion cycle in which all bit values of the conversion result output value are generated.
5. The semiconductor device according to claim 2 , wherein the offset control circuit updates the offset control value when the number of conversion cycles in which output values of all bits of the conversion result output value are generated reaches a preset number of cycles.
6. The semiconductor device according to claim 5 , wherein the offset control circuit changes the number of cycles every time the offset control circuit updates the offset control value.
7. The semiconductor device according to claim 5 , wherein the offset control circuit determines a direction in which the offset control value is changed, according to a ratio between the number of positive determinations and the number of negative determinations, the positive determinations and the negative determinations being included in an integrated value of values indicated by the offset determination signal corresponding to the preset number of cycles.