Top gate TFT with polymer interface control layer
View Patent ↗A transistor includes a substrate and a polymer layer that is in contact with the substrate. The polymer layer has a first pattern defining a first area. There is an inorganic semiconductor layer over and in contact with the polymer layer that has a second pattern defining a second area. The first area is located within the second area. There is a source electrode in contact with a first portion of the semiconductor layer and a drain electrode in contact with a second portion of the semiconductor layer, and the source electrode and the drain electrode separated by a gap. A gate insulating layer is in contact with the inorganic semiconductor layer in the gap. There is a gate in contact with the gate insulating layer over the gap.
1. A transistor comprising:
a substrate;
an electrically insulating polymer layer in contact with the substrate, the electrically insulating polymer layer having a first pattern defining a first area;
an inorganic semiconductor layer over and in contact with the electrically insulating polymer layer and having a second pattern defining a second area, the first area located within the second area;
a source electrode in contact with a first portion of the semiconductor layer;
a drain electrode in contact with a second portion of the semiconductor layer, the source electrode and the drain electrode separated by a gap;
a gate insulating layer in contact with the inorganic semiconductor layer in the gap; and
a gate in contact with the gate insulating layer over the gap.
2. The transistor of claim 1 , wherein the first pattern and the second pattern are the same.
3. The transistor of claim 1 , wherein the first area is smaller than the second area.
4. The transistor of claim 1 , wherein the first pattern defines the gap that separates the source electrode and the drain electrode.
5. The transistor of claim 4 , wherein the source electrode and the drain electrode are not over the electrically insulating polymer layer.
6. The transistor of claim 1 , wherein at least a portion of each of the source electrode and the drain electrode are over at least a portion of the electrically insulating polymer layer and the semiconductor layer.
7. The transistor of claim 1 , wherein the inorganic semiconductor is a metal oxide semiconductor.
8. The transistor of claim 7 , wherein the metal oxide semiconductor is a ZnO based semiconductor.
9. The transistor of claim 1 , wherein the substrate is an inorganic substrate.
10. The transistor of claim 1 , wherein the first area is at least 90% of the second area.
11. The transistor of claim 1 , wherein the first area is at least 95% of the second area.