Differential mode bandwidth extension technique with common mode compensation
A method and apparatus are provided. The apparatus may be a capacitive element for adjusting a net capacitance of a circuit. The apparatus may be configured to be coupled to the circuit. The apparatus may be configured to adjust the net capacitance of the circuit to decouple common mode and differential loop bandwidth adjustment of the circuit. The capacitive element may include a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit, and a pair of negative gain buffers coupled to respective capacitors.
1. An apparatus comprising:
a capacitive element configured to adjust a net capacitance of a circuit, wherein the capacitive element comprises:
a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit; and
a pair of negative gain buffers coupled to respective capacitors, wherein the capacitive element is configured to have a positive capacitance to stabilize a common mode feedback loop of the circuit in a common mode.
2. The apparatus of claim 1 , wherein the capacitive element is configured to have a negative capacitance to at least partially negate a parasitic capacitance of the circuit in a differential mode, and is configured to extend a differential loop bandwidth of the circuit.
3. The apparatus of claim 2 , wherein the parasitic capacitance is at one or more differential nodes of the circuit.
4. The apparatus of claim 1 , wherein the capacitive element is configured to be coupled to a transconductance circuit as the circuit.
5. The apparatus of claim 4 , wherein the negative gain buffers are tunable.
6. The apparatus of claim 5 , wherein a gain factor of each of the negative gain buffers is less than −1 when the circuit is in either differential or common mode.
7. The apparatus of claim 4 , wherein each of the negative gain buffers comprises:
a first transistor comprising a source electrode, a drain electrode, and a gate electrode coupled to the drain electrode; and
a plurality of second transistors coupled in parallel, each of the second transistors comprising a drain electrode coupled to the source electrode of the first transistor, and a source electrode coupled to ground.
8. A method for decoupling common mode and differential loop bandwidth adjustment of a circuit, the method comprising:
increasing, with a capacitive element, a capacitance of the circuit in a common mode,
wherein the capacitive element comprises:
a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit; and
a pair of negative gain buffers coupled to respective capacitors,
wherein the capacitive element is increased to a positive capacitance to stabilize a common mode feedback loop of the circuit in a common mode.
9. The method of claim 8 , further comprising negating, with the capacitive element, at least a portion of parasitic capacitance of the circuit in a differential mode.
10. The method of claim 9 , wherein the negating and the increasing comprise tuning the negative gain buffers of the capacitive element.
11. The method of claim 9 , wherein the negating comprises tuning one or more of the negative gain buffers to have a gain factor of less than −1, and
wherein the increasing comprises tuning one or more of the negative gain buffers to have a gain factor of less than 0.
12. The method of claim 9 , wherein each of the negative gain buffers comprises:
a first transistor comprising:
a source electrode;
a drain electrode; and
a gate electrode coupled to the drain electrode; and
a plurality of second transistors coupled in parallel, each of the second transistors comprising:
a drain electrode coupled to the source electrode of the first transistor;
a source electrode coupled to ground; and
a gate electrode,
wherein the negating and the increasing comprise tuning the negative gain buffers of the capacitive element by providing a signal to the gate of one or more selected second transistors.
13. The method of claim 8 , wherein the circuit is a transconductance circuit.
14. An apparatus for decoupling common mode and differential loop bandwidth adjustment of a circuit, comprising
means for adjusting, with a capacitive element, a net capacitance of the circuit, the capacitive element comprising:
a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit; and
a pair of negative gain buffers coupled to respective capacitors,
wherein, when the circuit is in a common mode, the means for adjusting are configured to:
have a positive capacitance to increase the net capacitance, and
stabilize a common mode feedback loop of the circuit.
15. The apparatus of claim 14 , wherein, when the circuit is in a differential mode, the means for adjusting are configured to:
have a negative capacitance;
at least partially negate a parasitic capacitance of the circuit to reduce the net capacitance; and
extend a differential loop bandwidth of the circuit.
16. The apparatus of claim 14 , wherein the capacitive element comprises means for adjusting, using the pair of cross-coupled capacitors and the pair of negative gain buffers, a bandwidth or a phase margin of the circuit.
17. The apparatus of claim 16 , further comprising means for tuning, in the negative gain buffers, a gain factor of the negative gain buffers.
18. The apparatus of claim 17 , wherein the means for tuning the gain factor of each of the negative gain buffers are configured to tune the gain factor to less than 0 when the circuit is in a common mode, and are configured to tune the gain factor to less than −1 when the circuit is in a differential mode.
19. The apparatus of claim 17 , wherein each of the negative gain buffers comprises:
a first transistor comprising:
a source electrode;
a drain electrode; and
a gate electrode coupled to the drain electrode; and
a plurality of second transistors coupled in parallel, each of the second transistors comprising:
a drain electrode coupled to the source electrode of the first transistor; and
a source electrode coupled to ground,
wherein the means for tuning comprise the plurality of second transistors.
20. The apparatus of claim 14 , wherein the circuit is a transconductance circuit.
21. An apparatus comprising:
a capacitive element configured to adjust a net capacitance of a circuit, wherein the capacitive element comprises:
a pair of cross-coupled transistors, each comprising:
a source electrode coupled to ground;
a drain electrode; and
a gate electrode;
a pair of capacitors, each comprising:
a first electrode coupled to the drain electrode of a respective one of the cross-coupled transistors; and
a second electrode coupled to the gate electrode of an opposite respective one of the cross-coupled transistors; and
a pair of diode-connected transistors, each comprising a source electrode coupled to the drain electrode of the respective one of the cross-coupled transistors.
22. An apparatus comprising:
a capacitive element configured to adjust a net capacitance of a circuit, wherein the capacitive element comprises:
a pair of cross-coupled capacitors configured to be coupled to differential nodes of the circuit; and
a pair of negative gain buffers coupled to respective capacitors,
wherein each of the negative gain buffers comprises:
a first transistor comprising a source electrode, a drain electrode, and a gate electrode coupled to the drain electrode; and
a plurality of second transistors coupled in parallel, each of the second transistors comprising a drain electrode coupled to the source electrode of the first transistor, and a source electrode coupled to ground.