IP Library Granted Patent US 9,384,137
Granted Patent B2
US 9,384,137 · App. 14/489,927 · Granted Jul 5, 2016

Progressive pre-caching

Inventor: Jason Caulkins (Issaquah, WA)
Assignee: DATARAM, Inc.
G06F12/0862G06F12/0871G06F12/12G06F2212/1016G06F2212/2515G06F2212/305G06F2212/601G06F2212/7201
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,384,137
App. No.
14/489,927
Granted
Jul 5, 2016
Kind
B2
Abstract

A system includes a computerized appliance connected to a network, a processor, a persistent memory, a dynamic random access memory, and software executing on the processor, the software provides for installing an application, storing data to be used in execution of the application, mapping logical block addresses at which particular data is stored to data in an order of expected use, the data-use profile listing an expected order of data use in execution of the application, configuring the DRAM with a cache of a specific data capacity, transferring a block of data equal to the cache size into the cache according to the order of data in the data-use profile, and as data is used in execution of the application, emptying used data from the cache and transferring not-yet-used data from persistent storage into the cache according to the order of data in the data-use profile.

Claims (25)

1. A system comprising:

a first computerized appliance having connection to a network, a processor, at least one persistent memory data repository coupled thereto, a dynamic random access memory (DRAM), and software (SW) executing on the processor from a non-transitory medium, the SW providing a process:

installing an application for which data caching is desired, storing data to be used in execution of the application at available persistent storage block addresses;

mapping logical block addresses at which particular data is stored to data in an order of expected use according to a data-use profile accessible to the installation process, the data-use profile listing an expected order of data use in execution of the application;

configuring the DRAM with a cache of a specific data capacity;

transferring a block of data equal to the cache size into the cache according to the order of data in the data-use profile; and

as data is used in execution of the application, emptying used data from the cache and transferring not-yet-used data from persistent storage into the cache according to the order of data in the data-use profile.

2. The system of claim 1 wherein data transfer into the cache is block-by-block in the order of the data-use profile as used data is evicted from the cache.

3. The system of claim 1 wherein data transfer into the cache is periodic and determined by pre-determined time or data size.

4. The system of claim 1 wherein data called in execution that is not found in the cache is read from persistent storage.

5. The system of claim 1 wherein actual data use in execution of the application is tracked and compared to the data-use profile, and wherein periodic correction to the data-use profile is made accordingly.

6. The system of claim 1 wherein the data use profile is developed by tracking data use by one or more computerized appliances in execution of the application.

7. The system of claim 6 wherein the data-use profile is developed in cooperation with a vendor of the application.

8. A method comprising:

installing an application for which data caching is desired in persistent memory of a first computerized appliance having connection to a network, a processor, at least one persistent memory data repository coupled thereto, a dynamic random access memory (DRAM), and software (SW) executing on the processor from a non-transitory medium, storing data to be used in execution of the application at available persistent storage block addresses;

mapping logical block addresses at which particular data is stored to data in an order of expected use according to a data-use profile accessible to the installation process, the data-use profile listing an expected order of data use in execution of the application;

configuring the DRAM with a cache of a specific data capacity;

transferring a block of data equal to the cache size into the cache according to the order of data in the data-use profile; and

as data is used in execution of the application, emptying used data from the cache and transferring not-yet-used data from persistent storage into the cache according to the order of data in the data-use profile.

9. The method of claim 8 wherein data transfer into the cache is block-by-block in the order of the data-use profile as used data is evicted from the cache.

10. The method of claim 8 wherein data transfer into the cache is periodic and determined by pre-determined time or data size.

11. The method of claim 8 wherein data called in execution that is not found in the cache is read from persistent storage.

12. The method of claim 8 wherein actual data use in execution of the application is tracked and compared to the data-use profile, and wherein periodic correction to the data-use profile is made accordingly.

13. The method of claim 8 wherein the data use profile is developed by tracking data use by one or more computerized appliances in execution of the application.

14. The method of claim 13 wherein the data-use profile is developed in cooperation with a vendor of the application.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2017
From: DATARAM CORPORATION
To: DATARAM MEMORY
Reel/Frame 043797/0582 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2014
From: CAULKINS, JASON
To: DATARAM, INC.
Reel/Frame 033768/0876 →
Continuity (2)
Continuation In Part 14188304 · Feb 24, 2014
Related Publication 20150242325A1 · Aug 27, 2015