A-priori-probability-phase-estimation for digital phase-locked loops

1. A digital phase locked loop comprising:

a time-to-digital converter configured to generate a quantized value based on a local oscillator signal of a local oscillator and a reference signal of a reference clock; and

an estimator component configured to receive the quantized value and generate an estimation of a phase value from the quantized value as a function of a set of a-priori data related to the time-to-digital converter and boundaries of the quantized value.

2. The digital phase locked loop of claim 1 , further comprising:

a distribution component configured to determine the set of a priori data comprising a statistical distribution of input data to the time-to-digital converter that includes an expected phase with a phase error, and facilitate a reduction of a quantization error associated with the quantized value that is provided into a feedback loop based on the estimation.

3. The digital phase locked loop of claim 1 , wherein the estimator component is further configured to generate the estimation of the phase value from the quantized value as a function of the set of a priori data that comprise a required phase value and the boundaries derived from quantization levels of the time-to-digital converter.

4. The digital phase locked loop of claim 1 , wherein the estimator component is further configured to generate the estimation of the phase value as a minimum-mean-square-error estimation of an un-quantized phase amount to the quantized value.

5. The digital phase locked loop of claim 1 , further comprising:

a reduction component configured to reduce a quantization error of the quantized value that is inserted into a feedback loop coupled to the time-to-digital converter and the estimator component.

6. The digital phase locked loop of claim 5 , wherein the reduction component is further configured to reduce the quantization error as a function of a floor boundary and a ceiling boundary of an observed time-to-digital level from the quantized value as an output of the time-to-digital converter and an expected phase.

7. The digital phase locked loop of claim 1 , further comprising:

a ceiling component configured to determine a ceiling level of the boundaries as an approximate high output level that is observed from the time-to-digital converter for a current phase sample; and

a floor component configured to determine a floor level of the boundaries as an approximate low output level that is observed from the time-to-digital converter for the current phase sample.

8. The digital phase locked loop of claim 1 , wherein the estimator component is further configured to generate the phase value based on an estimation of an estimator component, and boundaries of an actual phase having a phase error as a statistical distribution about an expected phase, wherein the estimation of the phase value is further a function of the boundaries derived from quantization levels of the time-to-digital converter associated with the quantized value that comprise a ceiling level and a floor level along a center of gravity of the statistical distribution as a minimum error-power.

9. The digital phase locked loop of claim 1 , further comprising:

a reduction component configured to reduce a quantization error of the quantized value as a function of the estimation, wherein the estimation is a function of a set of a priori data comprising an expected phase, the actual phase comprising a statistical distribution of the expected phase with a phase error component and a position of a set of quantization levels of the time-to-digital converter associated with the quantized value.

10. The digital phase locked loop of claim 1 , wherein the estimator component is further configured to estimate an input of the time-to-digital converter that is a function of an expected phase and a phase noise of the local oscillator signal and the reference signal.

11. A method comprising:

receiving, via an estimator component, a quantized phase from a time-to-digital converter in a digital phase locked loop;

determining, via the estimator component, boundaries of an actual phase from the quantized phase; and

estimating a phase value based on an approximation process that estimates an input to the time-to-digital converter based on the boundaries of the actual phase and a set of a-priori data related to the time-to-digital converter.

12. The method of claim 11 , wherein the determining of the boundaries comprises determining a time-to-digital quantization level from among a number of a plurality of quantization levels of the time-to-digital converter and a ceiling level and a floor level of the actual phase.

13. The method of claim 11 , further comprising:

determining the actual phase as a random variable distribution about an expected phase of the digital phase locked loop; and

outputting the phase value to a digital loop filter of a control loop path.

14. The method of claim 13 , wherein the estimating of the phase value from the quantized phase is further based on the random variable distribution about the expected phase.

15. The method of claim 13 , further comprising:

generating a minimum-mean-square-error estimation of the random variable distribution about the expected phase with the boundaries to estimate the phase value or a phase offset from the expected phase.

16. The method of claim 11 , wherein the estimating the phase value comprises determining a statistical distribution of the a-priori information related to the time-to-digital converter as a part of the approximation process with respect to the boundaries of the actual phase.

17. The method of claim 11 , further comprising:

generating a correction to the quantized phase as a function of an estimation generated by the approximation process and inserting the correction into a control loop path of the digital phase locked loop.

18. The method of claim 17 , further comprising:

improving a performance to power ratio of the digital phase locked loop as a function of the correction by the estimation with a minimum error power.

19. The method of claim 11 , wherein the quantized phase is based on a number of quantization levels of the time-to-digital converter.

20. The method of claim 11 , further comprising:

determining a random variable distribution about an expected phase comprising a phase error as the input to the time-to-digital converter; and

performing a minimum-mean-square-error estimation on the random variable distribution for estimating the phase value.

21. A mobile device comprising:

a digital phase locked loop circuit comprising:

a time-to-digital converter configured to generate a quantization output from a local oscillator signal of a local oscillator and a reference signal of a reference clock; and

an estimator component configured to generate an estimation of a phase value from the quantization output as a function of a set of a-priori data related to the time-to-digital converter and boundaries of the quantization output.

22. The mobile device of claim 21 , wherein the estimator component is further configured to generate the estimation as a function of the set of a-priori data that is related to quantization levels of the time-to-digital converter and a statistical distribution of an input to the time-to-digital converter.

23. The mobile device of claim 21 , wherein the estimator component generates a minimum-mean-square error estimation on a statistical distribution of a phase error inputted to the time-to-digital converter with the boundaries defined by the quantization output and a position of a plurality of quantization levels of the time-to-digital converter associated with the quantization output.

24. The mobile device of claim 21 , further comprising:

a reduction component configured to reduce a quantization error of the quantization output that is inserted into a closed loop as a function of a floor boundary and a ceiling boundary of an observed time-to-digital level from the quantization output from the time-to-digital converter and an expected phase value.

25. The mobile device of claim 21 , wherein the estimator component is further configured to generate the estimation of the phase value after the digital phase locked loop circuit becomes locked for generation of digital timing signals.