Address verification on a bus
Address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, including: receiving, by a receiving bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node; determining, by the receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node; responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal; and responsive to determining that the parity signal is not the expected parity signal, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal.
1. A method of address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, the method comprising:
receiving, by a receiving bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node, wherein the receiving bus node first receives the address signal as a plurality of bits on a signal line of the bus and, immediately following the address signal, receives the parity signal as at least one bit on the same signal line;
determining, by the receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node;
responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal, wherein values of the parity signal and the expected parity signal are determined based on an address of a corresponding receiving bus node;
responsive to determining that the address of the target receiving bus node does not match an address of the receiving bus node, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal; and
responsive to determining that both the address of the target receiving bus node matches an address of the receiving bus node and the parity signal is not the expected parity signal, suppressing, by the receiving bus node, the acknowledgment of receipt of the address signal.
2. The method of claim 1 further comprising responsive to determining that the parity signal is the expected parity signal, sending, by the receiving bus node to the sending bus node over the bus, an acknowledgment of receipt of the address signal.
3. The method of claim 1 further comprising determining, by the receiving bus node, a value of the expected parity signal in dependence upon the address of the receiving bus node.
4. The method of claim 1 further comprising determining, by the receiving bus node, a value of the expected parity signal in dependence upon a predetermined parity signal generation algorithm.
5. The method of claim 4 wherein determining whether the parity signal associated with the address signal is an expected parity signal further comprises comparing the received parity signal to the value of the expected parity signal.
6. The method of claim 1 wherein the bus is an I2C bus.
7. The method of claim 1 , wherein the address signal and the parity signal following the address signal is received on a serial data line of an I2C bus.
8. An apparatus for address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, the apparatus comprising a receiving bus node configured to perform the steps of:
receiving, by a receiving bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node, wherein the receiving bus node first receives the address signal as a plurality of bits on a signal line of the bus and, immediately following the address signal, receives the parity signal as at least one bit on the same signal line;
determining, by the receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node;
responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal, wherein values of the parity signal and the expected parity signal are determined based on an address of a corresponding receiving bus node;
responsive to determining that the address of the target receiving bus node does not match an address of the receiving bus node, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal; and
responsive to determining that both the address of the target receiving bus node matches an address of the receiving bus node and the parity signal is not the expected parity signal, suppressing, by the receiving bus node, the acknowledgment of receipt of the address signal.
9. The apparatus of claim 8 wherein the receiving bus node is further configured to perform the step of, responsive to determining that the parity signal is the expected parity signal, sending, by the receiving bus node to the sending bus node over the bus, an acknowledgment of receipt of the address signal.
10. The apparatus of claim 8 wherein the receiving bus node is further configured to perform the step of determining a value of the expected parity signal in dependence upon the address of the receiving bus node.
11. The apparatus of claim 8 wherein the receiving bus node is further configured to perform the step of determining a value of the expected parity signal in dependence upon a predetermined parity signal generation algorithm.
12. The apparatus of claim 8 wherein determining whether the parity signal associated with the address signal is an expected parity signal further comprises comparing the received parity signal to the value of the expected parity signal.
13. The apparatus of claim 8 wherein the bus is an I2C bus.
14. The apparatus of claim 8 , wherein the address signal and the parity signal following the address signal is received on a serial data line of an I2C bus.
15. A method of address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, the method comprising:
transmitting, by a sending bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node, wherein the sending bus node first transmits the address signal as a plurality of bits on a signal line of the bus and, immediately following the address signal, transmits the parity signal as at least one bit on the same signal line;
determining, by a receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node;
responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal, wherein values of the parity signal and the expected parity signal are determined based on an address of a corresponding receiving bus node;
responsive to determining that the address of the target receiving bus node does not match an address of the receiving bus node, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal;
responsive to determining that both the address of the target receiving bus node matches an address of the receiving bus node and the parity signal is not the expected parity signal, suppressing, by the receiving bus node, the acknowledgment of receipt of the address signal;
determining, by the sending bus node, whether at least one of the parity signal or the address signal were interfered with during transmission; and
responsive to determining that at least one of the parity signal and the address signal were interfered with during transmission, retransmitting, by the sending bus node over the bus, the parity signal and the address signal.
16. The method of claim 15 wherein determining whether at least one of the parity signal or the address signal were interfered with during transmission further comprises determining whether an acknowledgment of receipt of the address signal has not been received during a predetermined time period.
17. The method of claim 15 wherein the parity signal is transmitted after a communications start sequence and prior to transmitting the address signal.
18. The method of claim 15 further comprising determining a value of the parity signal in dependence upon the address of the target receiving bus node.
19. The method of claim 15 further comprising determining a value of the parity signal in dependence upon a predetermined parity signal generation algorithm.
20. The method of claim 15 wherein the bus is an I2C bus, and wherein the address signal and the parity signal following the address signal is received on a serial data line of the I2C bus.