Semiconductor integrated device for display drive
View Patent ↗In a display drive IC chip of an LCD or the like, an alignment mark is arranged in an alignment mark arrangement region on the main surface thereof, a dummy pattern is arranged on a lower layer, and an actual pattern is further arranged on the lower layer.
1. A semiconductor integrated device for display drive comprising:
(a) a chip-shaped semiconductor substrate having a first main surface;
(b) a large number of pad electrodes for bump electrode formation, provided on the first main surface side of the chip-shaped semiconductor substrate, which are constituted by a pad metal wiring layer;
(c) an alignment mark arrangement region provided on the first main surface side of the chip-shaped semiconductor substrate;
(d) an alignment mark, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by the pad metal wiring layer;
(e) an upper dummy wiring pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by an upper metal wiring layer located below the pad metal wiring layer; and
(f) an actual device pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by a lower device layer located below the upper metal wiring layer,
wherein the lower device layer comprises an element pattern contributing to a circuit configuration of the device.
2. The semiconductor integrated device for display drive according to claim 1 , wherein the lower device layer is a first intermediate metal wiring layer, and the actual device pattern is an intermediate actual wiring pattern.
3. The semiconductor integrated device for display drive according to claim 2 , further comprising:
(g) a lower actual wiring pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by a lower metal wiring layer located below the first intermediate metal wiring layer.
4. The semiconductor integrated device for display drive according to claim 3 , further comprising:
(h) a light shielding pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by a second intermediate metal wiring layer located below the upper metal wiring layer and located above the first intermediate metal wiring layer.
5. The semiconductor integrated device for display drive according to claim 4 , wherein the light shielding pattern is a line-and-space pattern.
6. The semiconductor integrated device for display drive according to claim 5 , wherein the intermediate actual wiring pattern is a power supply wiring pattern.
7. The semiconductor integrated device for display drive according to claim 6 , wherein the upper metal wiring layer, the first intermediate metal wiring layer, the second intermediate metal wiring layer and the lower metal wiring layer are copper-based buried wirings, respectively.
8. The semiconductor integrated device for display drive according to claim 7 , wherein the pad metal wiring layer is an aluminum-based non-buried wiring.
9. The semiconductor integrated device for display drive according to claim 8 , further comprising:
(i) a pad layer dummy wiring pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and in the vicinity of the alignment mark within the alignment mark arrangement region, which is constituted by the pad metal wiring layer.
10. The semiconductor integrated device for display drive according to claim 9 , further comprising:
(j) an actual gate electrode pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by a gate electrode layer located below the lower metal wiring layer; and
(k) an actual element isolation insulating film pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the alignment mark arrangement region, which is constituted by an element isolation insulating film layer located below the gate electrode layer.
11. A semiconductor integrated device for display drive comprising:
(a) a chip-shaped semiconductor substrate having a first main surface;
(b) a large number of pad electrodes for bump electrode formation, provided on the first main surface side of the chip-shaped semiconductor substrate, which are constituted by a pad metal wiring layer;
(c) an identification pattern arrangement region provided on the first main surface side of the chip-shaped semiconductor substrate;
(d) an identification pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the identification pattern arrangement region, which is constituted by the pad metal wiring layer;
(e) an upper dummy wiring pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the identification pattern arrangement region, which is constituted by an upper metal wiring layer located below the pad metal wiring layer; and
(f) an actual device pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the identification pattern arrangement region, which is constituted by a lower device layer located below the upper metal wiring layer,
wherein the lower device layer comprises an element pattern contributing to a circuit configuration of the device.
12. The semiconductor integrated device for display drive according to claim 11 , wherein the lower device layer is a first intermediate metal wiring layer, and the actual device pattern is an intermediate actual wiring pattern.
13. The semiconductor integrated device for display drive according to claim 12 , further comprising:
(g) a lower actual wiring pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the identification pattern arrangement region, which is constituted by a lower metal wiring layer located below the first intermediate metal wiring layer.
14. The semiconductor integrated device for display drive according to claim 13 , further comprising:
(h) alight shielding pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the identification pattern arrangement region, which is constituted by a second intermediate metal wiring layer located below the upper metal wiring layer and located above the first intermediate metal wiring layer.
15. The semiconductor integrated device for display drive according to claim 14 , wherein the light shielding pattern is a line-and-space pattern.
16. The semiconductor integrated device for display drive according to claim 15 , wherein the intermediate actual wiring pattern is a power supply wiring pattern.
17. The semiconductor integrated device for display drive according to claim 16 , wherein the upper metal wiring layer, the first intermediate metal wiring layer, the second intermediate metal wiring layer and the lower metal wiring layer are copper-based buried wirings, respectively.
18. The semiconductor integrated device for display drive according to claim 17 , wherein the pad metal wiring layer is an aluminum-based non-buried wiring.
19. The semiconductor integrated device for display drive according to claim 18 , further comprising:
(i) a pad layer dummy wiring pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and in the vicinity of the identification pattern within the identification pattern arrangement region, which is constituted by the pad metal wiring layer.
20. The semiconductor integrated device for display drive according to claim 19 , further comprising:
(j) an actual gate electrode pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the identification pattern arrangement region, which is constituted by a gate electrode layer located below the lower metal wiring layer; and
(k) an actual element isolation insulating film pattern, provided on the first main surface side of the chip-shaped semiconductor substrate and within the identification pattern arrangement region, which is constituted by an element isolation insulating film layer located below the gate electrode layer.