RF SOI switch with backside cavity and the method to form it
View Patent ↗An integrated circuit includes a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer, a transistor disposed on the second semiconductor substrate and having a bottom insulated by the insulating layer, a plurality of shallow trench isolations disposed on opposite sides of the transistor, a cavity disposed below the bottom of the transistor, and a plurality of isolation plugs disposed on opposite sides of the cavity. By having a cavity located below the transistor, parasitic couplings between the transistor and the substrate are reduced and the performance of the integrated circuit is improved.
1. An integrated circuit comprising:
a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer;
a transistor disposed on and in the second semiconductor substrate and having a bottom portion insulated by the insulating layer;
a plurality of shallow trench isolations disposed on opposite sides of the transistor,
a cavity disposed below the bottom portion of the transistor; and
a plurality of isolation plugs disposed on opposite sides of the cavity;
wherein the cavity is disposed on an upper portion of the first semiconductor substrate and comprises a top surface delineated by the insulating layer.
2. The integrated circuit of claim 1 , wherein the cavity has a height in a range between 0.1 um and 10 um.
3. The integrated circuit of claim 2 , where the height is in a range between 1 um and 2 um.
4. An integrated circuit comprising:
a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer;
a transistor disposed on and in the second semiconductor substrate and having a bottom portion insulated by the insulating layer;
a plurality of shallow trench isolations disposed on opposite sides of the transistor,
a cavity disposed below the bottom portion of the transistor; and
a plurality of isolation plugs disposed on opposite sides of the cavity;
wherein an isolation plug is formed through a shallow trench isolation and the insulating layer and comprises a lower end within the first semiconductor substrate.
5. The integrated circuit of claim 4 , wherein an isolation plug comprises a silicon oxide material, a fluorine-doped silicate glass material, a high-density plasma oxide material, or a low-k dielectric material.
6. The integrated circuit of claim 4 , further comprising a dielectric layer overlying the transistor and insulating a top surface of the transistor.
7. The integrated circuit of claim 6 , wherein the dielectric layer comprises a silicon oxide material, a fluorine-doped silicate glass material, a high-density plasma oxide material, or a low-k dielectric material.
8. The integrated circuit of claim 6 , wherein the dielectric layer is formed of a same material as the isolation plugs.
9. The integrated circuit of claim 4 , wherein the integrated device is a radio frequency switching device, or a radio frequency front-end module.
10. The integrated circuit of claim 9 , wherein the transistor is a transistor of the radio frequency switching device.
11. An electronic device comprising an integrated circuit, wherein the integrated circuit comprises:
a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor substrate, and a second semiconductor substrate on the insulating layer;
a transistor disposed on and in the second semiconductor substrate and having a bottom portion insulated by the insulating layer;
a plurality of shallow trench isolations disposed on opposite sides of the transistor,
a cavity disposed below the bottom portion of the transistor, the cavity extending through a space below the bottom portion of the whole transistor; and
a plurality of isolation plugs disposed on opposite sides of the cavity.
12. The electronic device of claim 11 , wherein the cavity is disposed on an upper portion of the first semiconductor substrate and comprises a top surface isolated by the insulating layer.
13. The electronic device of claim 11 , wherein the cavity is disposed in the first semiconductor substrate and has a height in a range between 0.1 um and 10 um.
14. The electronic device of claim 11 , wherein an isolation plug is formed through a shallow trench isolation and the insulating layer and comprises a lower end within the first semiconductor substrate.