IP Library Granted Patent US 9,740,632
Granted Patent B1
US 9,740,632 · App. 14/496,359 · Granted Aug 22, 2017

Snapshot efficiency

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Quick Facts
Patent No.
US 9,740,632
App. No.
14/496,359
Granted
Aug 22, 2017
Kind
B1
Abstract

In one aspect, a method includes receiving a request to write to an offset in a first logical device, determining a second logical device that wrote to the offset, the second logical device being an ancestor of the first logical device in a hierarchical tree of snapshots, determining from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data, removing address-to-hash mapping for the offset of the second logical device if the data for the offset is shadowed and moving address-to-hash mapping to a single descendent of the second logical device if the data for the offset is partially shadowed.

Claims (33)

1. A method comprising:

receiving a plurality of write request requests to write to an offset in a first logical device;

determining, for each write request received, a second logical device that wrote to the offset, the second logical device being an ancestor of the first logical device in a hierarchical tree of snapshots;

determining, for each write request received, from descendants of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data;

and for each write request received, removing an address-to-hash mapping for the offset of the second logical device if the data for the offset is shadowed; and moving the address-to-hash mapping to a single descendant that has sole access to the offset of the second logical device if the data for the offset is partially shadowed.

2. The method of claim 1 , wherein determining a second logical device that wrote to the offset comprises ascending the hierarchical tree from the first logical device to determine a second logical device that is the first to write to the offset.

3. The method of claim 1 , wherein determining a second logical device that wrote to the offset comprises determining a second logical device that wrote to the offset using a bitmap of the offset.

4. The method of claim 1 , wherein determining from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data comprises determining from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data using a bitmap of the offset.

5. The method of claim 1 , wherein data in the offset of the second logical device is shadowed data if no external device may access the data in the offset of the second logical unit.

6. The method of claim 1 , wherein data in the offset of the second logical device is partially shadowed data if only one external device may access the data in the offset of the second logical unit.

7. An apparatus, comprising:

electronic hardware circuitry configured to:

receive a plurality of write requests to write to an offset in a first logical device;

determine, for each write request, a second logical device that wrote to the offset, the second logical device being an ancestor of the first logical device in a hierarchical tree of snapshots;

determine, for each write request, from descendants of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data;

and for each write request received, remove an address-to-hash mapping for the offset of the second logical device if the data for the offset is shadowed; and move the address-to-hash mapping to a single descendent that has sole access to the offset of the second logical device if the data for the offset is partially shadowed.

8. The apparatus of claim 7 , wherein the circuitry comprises at least one of a processor, a memory, a programmable logic device or a logic gate.

9. The apparatus of claim 7 , wherein the circuitry configured to determine a second logical device that wrote to the offset comprises circuitry configured to ascend the hierarchical tree from the first logical device to determine a second logical device that is the first to write to the offset.

10. The apparatus of claim 7 , wherein the circuitry configured to determine a second logical device that wrote to the offset comprises circuitry configured to determine a second logical device that wrote to the offset using a bitmap of the offset.

11. The apparatus of claim 7 , wherein the circuitry configured to determine from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data comprises circuitry configured to determine from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data using a bitmap of the offset.

12. The apparatus of claim 7 , wherein data in the offset of the second logical device is shadowed data if no external device may access the data in the offset of the second logical unit.

13. The apparatus of claim 7 , wherein data in the offset of the second logical device is partially shadowed data if only one external device may access the data in the offset of the second logical unit.

14. An article comprising:

a non-transitory computer-readable medium that stores computer-executable instructions the instructions causing a machine to:

receive a plurality of write requests to write to an offset in a first logical device;

determine, for each write request, a second logical device that wrote to the offset, the second logical device being an ancestor of the first logical device in a hierarchical tree of snapshots;

determine, for each write request, from descendants of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data;

and for each write request received, remove an address-to-hash mapping for the offset of the second logical device if the data for the offset is shadowed; and move the address-to-hash mapping to a single descendent that has sole access to the offset of the second logical device if the data for the offset is partially shadowed.

15. The article of claim 14 , wherein the instructions causing the machine to determine a second logical device that wrote to the offset comprises instructions causing the machine to ascend the hierarchical tree from the first logical device to determine a second logical device that is the first to write to the offset.

16. The article of claim 14 , wherein the instructions causing the machine to determine a second logical device that wrote to the offset comprises instructions causing the machine to determine a second logical device that wrote to the offset using a bitmap of the offset.

17. The article of claim 14 , wherein the instructions causing the machine to determine from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data comprises instructions causing the machine to determine from decedents of the second logical device in the hierarchical tree whether data in the offset of the second logical device is shadowed data or partially shadowed data using a bitmap of the offset.

18. The article of claim 14 , wherein data in the offset of the second logical device is shadowed data if no external device may access the data in the offset of the second logical unit.

19. The article of claim 14 , wherein data in the offset of the second logical device is partially shadowed data if only one external device may access the data in the offset of the second logical unit.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (044535/0109) Recorded May 20, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 060753/0414 →
RELEASE OF SECURITY INTEREST AT REEL 044535 FRAME 0001 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058298/0475 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY AGREEMENT (NOTES) Recorded Nov 29, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 044535/0109 →
PATENT SECURITY AGREEMENT (CREDIT) Recorded Nov 29, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 044535/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 25, 2014
From: LOVE, PHIL; LEMPEL, IRIT; HALEVI, IDO; SHOIKHET, KIRILL; HALLAK, RENEN
To: EMC CORPORATION
Reel/Frame 034257/0663 →