Gain calibration of ADC residue amplifiers

1. A device for gain calibration of an analog-to-digital converter (ADC) residue amplifier, the device comprising:

a digital-to analog converter (DAC) configured to convert a digital signal to an analog signal, the DAC including a calibration means configured for being used in the gain calibration of the ADC residue amplifier; and

a flash ADC configured to generate the digital signal, the flash ADC including a plurality of comparators and an additional comparator,

wherein a count of the plurality of comparators is equal to a number of output bits of the flash ADC and the additional comparator is configured to provide a threshold voltage approximately in a middle point of a nominal subrange, wherein the nominal subrange comprises a portion of a voltage range corresponding to threshold voltages of two adjacent comparators of the plurality of comparators.

2. The device of claim 1 , wherein the flash ADC is configured to generate the digital signal by conversion to digital of a sample of an input signal.

3. The device of claim 2 , wherein the device comprises a part of a stage of a pipeline ADC that includes the ADC residue amplifier that is configured to amplify a residue signal.

4. The device of claim 3 , wherein the residue signal is created by subtraction of the analog signal from the sample of the input signal.

5. The device of claim 1 , wherein the DAC comprises a multiplying DAC (MDAC), wherein the calibration means includes a calibration capacitor, and wherein during a phase of a clock signal the calibration capacitor is charged by a reference voltage.

6. The device of claim 5 , wherein the calibration capacitor is configured to be charged to a voltage level that is approximately equal to half of the nominal subrange, and wherein the threshold voltage provided by the additional comparator is set to prevent an adverse effect of a calibration signal on a dynamic range of the ADC residue amplifier.

7. The device of claim 1 , wherein the gain calibration of the ADC comprises a background calibration, wherein the background calibration is performed by injection of a calibration signal to the DAC.

8. The device of claim 7 , wherein the injection of the calibration signal is controlled by a pseudo-random bit sequence (PRBS) and is allowed when an amplitude of the input signal is larger than the threshold voltage of the additional comparator.

9. The device of claim 7 , wherein the flash ADC comprises other additional comparators, and wherein the injection of the calibration signal is allowed when the amplitude of the input signal is larger than a threshold voltage of one of the other additional comparators.

10. A method for gain calibration of an analog-to-digital converter (ADC) residue amplifier, the method comprising:

generating a digital signal by using a flash ADC including a plurality of comparators and an additional comparator, wherein a count of the plurality of comparators is equal to a number of output bits of the flash ADC;

converting the digital signal to an analog signal, using a digital-to analog converter (DAC);

configuring the additional comparator to provide a threshold voltage approximately in a middle point of a nominal subrange, wherein the nominal subrange comprises a portion of a voltage range corresponding to threshold voltages of two adjacent comparators of the plurality of comparators; and

calibrating a gain of the ADC residue amplifier using a calibration signal.

11. The method of claim 10 , further comprising using flash ADC to convert to digital a sample of an input signal to generate the digital signal.

12. The method of claim 11 , wherein the flash ADC and the DAC comprise parts of a stage of a pipeline ADC that includes the ADC residue amplifier, and wherein the method comprises configuring the ADC residue amplifier to amplify a residue signal.

13. The method of claim 12 , further comprising creating the residue signal by subtraction of the analog signal from the sample of the input signal.

14. The method of claim 10 , wherein the DAC comprises a multiplying DAC (MDAC), and wherein the method further comprises generating a calibration signal by charging a calibration capacitor by using a reference voltage during a phase of a clock signal.

15. The method of claim 14 , further comprising:

choosing a capacitance value for the calibration capacitor that allows charging of the calibration capacitor to a voltage level that is approximately equal to half of the nominal subrange, and

setting the threshold voltage provided by the additional comparator to prevent an adverse effect of the calibration signal on a dynamic range of the ADC residue amplifier.

16. The method of claim 10 , wherein calibrating the gain of the ADC comprises performing a background calibration, and wherein performing the background calibration comprises injection of a calibration signal to the DAC.

17. The method of claim 16 , further comprising controlling the injection of the calibration signal by using a pseudo-random bit sequence (PRBS) and allowing the injection of the calibration signal when an amplitude of the input signal is larger than the threshold voltage of the additional comparator.

18. The method of claim 16 , wherein the flash ADC comprises other additional comparators, and wherein the method further comprises allowing the injection of the calibration signal when the amplitude of the input signal is larger than a threshold voltage of one of the other additional comparators.

19. A communication device comprising:

a pipeline ADC comprising a plurality of stages, at least some of the stages comprising:

a digital-to analog converter (DAC) configured to convert a digital signal to an analog signal;

a flash ADC configured to generate the digital signal, the flash ADC including a plurality of comparators and an additional comparator, wherein a count of the plurality of comparators is equal to a number of output bits of the flash ADC; and

a residue amplifier configured to be calibrated by using a calibration signal,

wherein the additional comparator is configured to provide a threshold voltage approximately in a middle point of a nominal subrange, and wherein the nominal subrange comprises a portion of a voltage range corresponding to threshold voltages of two adjacent comparators of the plurality of comparators.

20. The communication device of claim 19 , wherein:

the flash ADC is configured to generate the digital signal by conversion to digital of a sample of an input signal,

the residue amplifier is configured to amplify a residue signal that is created by subtraction of the analog signal from the sample of the input signal,

during a phase of a clock signal, the calibration signal is generated by a calibration capacitor that is charged by a reference voltage to a voltage level that is approximately equal to half of the nominal subrange, and

the threshold voltage provided by the additional comparator is set to prevent an adverse effect of the calibration signal on a dynamic range of the ADC residue amplifier.