Method for making an integrated circuit
A method includes making a gate stack on the surface of an active zone, including depositing a first dielectric layer; depositing a gate conductive layer; depositing a first metal layer; depositing a second metal layer; depositing a second dielectric layer; partially etching the gate stack for the formation of a gate zone on the active zone; making insulating spacers on either side of the gate zone on the active zone; making source and drain electrodes zones; making silicidation zones on the surface of the source and drain zones; etching, in the gate zone on the active zone, the second dielectric layer and the second metal layer with stopping on the first metal layer, so as to form a cavity between the insulating spacers; making a protective plug at the surface of the first metal layer of the gate zone on the active zone, where the protective plug fills the cavity.
1. A method for making an integrated circuit on a substrate, comprising:
making a gate stack on a surface of an active zone, the making comprising:
depositing a layer of first dielectric which extends over the active zone;
depositing a gate conductive layer which extends over the layer of first dielectric;
depositing a layer of a first metal which extends over the gate conductive layer;
depositing a layer of a second metal which extends over the layer of the first metal;
depositing a layer of a second dielectric which extends over the layer of the second metal;
partially etching the gate stack for the formation of a gate zone on the active zone;
making insulating spacers on either side of the gate zone on the active zone;
making source and drain zones;
making silicidation zones on a surface of the source and drain zones;
etching, in the gate zone on the active zone, the second dielectric layer and the layer of second metal with stopping on the layer of the first metal, so as to form a cavity between the insulating spacers; and
making a protective plug at a surface of the layer of first metal of the gate zone on the active zone, wherein the protective plug fills the cavity.
2. The method according to claim 1 , wherein the layer of the first metal is a layer made of an alloy of refractory metal.
3. The method according to claim 2 , wherein the layer of the first metal is a layer made of one of the following materials:
an alloy of Titanium Ti;
an alloy of Tungsten W;
an alloy of Tantalum Ta;
an alloy of a metal and silicon Si.
4. The method according to claim 1 , wherein the layer of the second metal is a layer made of an alloy of refractory metal.
5. The method according to claim 4 , wherein the layer of the second metal is a layer made of one of the following materials:
an alloy of Titanium Ti;
an alloy of Tungsten W;
an alloy of Tantalum Ta.
6. The method according to claim 1 , wherein the first metal in the layer of the first metal is different from the second metal in the layer of the second metal.
7. The method according to claim 6 , wherein the layer of the second metal may be selectively etched in relation to the layer of the first metal.
8. The method according to claim 7 , wherein the etching selectivity ratio between the layer of the second metal and the layer of the first metal is greater than 5:1.
9. The method according to claim 1 , wherein the layer of the first metal has a thickness greater than or equal to 15 nm.
10. The method according to claim 1 , wherein the layer of the second metal has a thickness of between 20 nm and 50 nm.
11. The method according to claim 1 , wherein the gate conductive layer has a thickness greater than or equal to 15 nm.
12. The method according to claim 1 , wherein a cumulative thickness of the gate conductive layer and of the layer of the first metal is less than or equal to 100 nm.
13. The method according to claim 1 , comprising:
depositing a conductive layer over the entire device; and
polishing the conductive layer in order to break the circuit between the source and drain silicidation zones.
14. The method according to claim 13 , comprising:
depositing a stop layer over the entire device;
depositing a layer of a dielectric on the stop layer;
selectively etching the layer of dielectric and the stop layer to expose the conductive layer, so as to cut trenches above the source and drain silicidation zones; and
filling said trenches with a conductive material in order to make contacts on the source and drain silicidation zones.
15. The method according to claim 1 , wherein the dielectric plug is made of a dielectric material including silicon nitride SiN, boron nitride BN or hafnium oxide HfO 2 .