Semiconductor device and process
A metal first, via first process for forming interconnects within a metallization layer of a semiconductor device is provided. In an embodiment a conductive material is deposited and the conductive material is patterned into a conductive line and a via. A dielectric material is deposited over the conductive line and the via, and the dielectric material and the via are planarized.
1. A semiconductor device comprising:
a conductive line over a substrate, wherein the conductive line extends a first distance from the substrate;
a via over the substrate, wherein a bottom surface of the via and a bottom surface of the conductive line are substantially planar, wherein the via comprises a first material that extends from the substrate a second distance larger than the first distance;
a liner in physical contact with the conductive line, the via, and the substrate, wherein the liner continuously extends from the conductive line to the via, wherein the liner has a thickness of between about 50 Å to about 500 Å; and
a dielectric over the conductive line and between the conductive line and the via, wherein the dielectric comprises a first material that extends throughout the dielectric.
2. The semiconductor device of claim 1 , further comprising air gaps located at least partially within the dielectric between the conductive line and the via.
3. The semiconductor device of claim 1 , further comprising an etch stop layer over the dielectric, wherein a top surface of the etch stop layer is substantially planar with a top surface of the via.
4. The semiconductor device of claim 3 , wherein the top surface of the etch stop layer is substantially planar with a top surface of the dielectric.
5. The semiconductor device of claim 1 , wherein the first material is copper.
6. A semiconductor device comprising:
a via in physical contact with a substrate, wherein the via comprises a first material throughout the via, wherein the via has a first width adjacent to the substrate and a second width smaller than the first width at a top surface of the via;
a conductive line in physical contact with the substrate, wherein the conductive line has a thickness that is less than the via; and
a dielectric layer covering the conductive line and adjacent to sidewalls of the via, wherein a first material of the dielectric layer extends from between the via and the conductive line and over the conductive line.
7. The semiconductor device of claim 6 , further comprising air gaps within the first material, wherein the air gaps are at least partially located between the via and the conductive line.
8. The semiconductor device of claim 6 , wherein the via has a straight sidewall that extends from a top of the via to a bottom of the via.
9. The semiconductor device of claim 6 , wherein the via and the conductive line are copper.
10. The semiconductor device of claim 6 , further comprising a liner stretching between the via and the conductive line, the liner is contact with the substrate.
11. The semiconductor device of claim 6 , further comprising an etch stop layer over the conductive line, wherein a top surface of the etch stop layer is substantially planar with a top surface of the via.
12. The semiconductor device of claim 11 , wherein the top surface of the etch stop layer is substantially planar with a top surface of the dielectric layer.
13. A semiconductor device comprising:
a conductive line in physical contact with a first surface of a substrate;
a via in physical contact with the first surface of the substrate, wherein the via extends further from the first surface than the conductive line;
a liner in physical contact with a surface of the conductive line and also in physical contact with a sidewall of the via, wherein a surface of the liner facing away from the via is conformal with the via and wherein the surface of the conductive line faces away from the substrate; and
a continuous dielectric material extending from a first region to a second region, wherein the first region is directly over the conductive line and the second region is located between the conductive line and the via and wherein the dielectric material comprises a constant composition throughout the dielectric material.
14. The semiconductor device of claim 13 , further comprising an air gap located within the second region.
15. The semiconductor device of claim 13 , wherein the liner has a top surface facing away from the substrate that is planar with a top surface of the via.
16. The semiconductor device of claim 15 , further comprising an etch stop layer over the dielectric material, wherein a top surface of the etch stop layer faces away from the substrate and is planar with the via.
17. The semiconductor device of claim 16 , wherein the etch stop layer is separated from the liner by the dielectric material.
18. The semiconductor device of claim 13 , wherein the via has a height of between about 10 nm and about 500 nm.
19. The semiconductor device of claim 13 , wherein the via is separated from the conductive line by an opening, the opening having a width of between about 10 nm and about 500 nm.
20. The semiconductor device of claim 13 , wherein the conductive line has a height of between about 200 Å and about 5000 Å.