On-die termination control without a dedicated pin in a multi-rank system
A memory subsystem includes a multi-device package including multiple memory devices organized as multiple ranks of memory. A control unit for the memory subsystem sends a memory access command concurrently to some or all of the ranks of memory, and triggers some of all of the memory ranks that receive the memory access command to change on-die termination (ODT) settings. One of the ranks is selected to execute the memory access command, and executes the command while all ranks triggered to change the ODT setting have the changed ODT setting.
1. A method for selectively applying on-die termination, comprising:
sending write command concurrently to multiple ranks of memory devices for a write operation in a multi-rank memory, the write command directed to a target rank of memory devices to execute the command, including sending multiple sequential commands to generate the write operation;
triggering, without an ODT control pin, target memory devices of the target rank to turn on on-die termination (ODT) for the write operation, including sending a first command indicating the write operation and a second command with a column address selection for the write operation, where the sequence of the first and second commands is to indicate an ODT setting to the ranks; and
selecting the target rank to execute the write operation.
2. The method of claim 1 , wherein triggering the target memory devices of the target rank to turn on ODT comprises triggering the target rank to engage ODT in accordance with an ODT value set in a Mode Register.
3. The method of claim 1 , wherein sending the write command comprises sending the write command from a memory controller integrated on a system on a chip with a processor.
4. The method of claim 1 , wherein the first command comprises either a Write-1 command or a Mask Write-1 command.
5. The method of claim 1 , wherein sending the first command triggers the target DRAM devices to engage ODT for the write operation.
6. The method of claim 1 , wherein triggering the target DRAM devices of the target rank to turn on ODT comprises triggering the target DRAM devices to change an ODT setting to one of multiple values of on-die termination resistance.
7. The method of claim 1 , wherein selecting the target rank comprises selecting the target rank with an enable signal.
8. The method of claim 7 , wherein selecting the target rank with the enable signal comprises selecting the target rank with a chip select signal.
9. A memory controller device comprising:
hardware connectors to couple to a multi-device package having multiple dynamic random access memory (DRAM) devices organized as a plurality of ranks; and
logic to
send a write command concurrently to multiple ranks of DRAM devices for a write operation, the write command directed to a target rank of DRAM devices to execute the command, including to send multiple sequential commands to generate the write operation;
trigger, without an ODT control pin, target DRAM devices of the target rank to turn on on-die termination (ODT) for the write operation, including sending a first command indicating the write operation and a second command with a column address selection for the write operation, where the sequence of the first and second commands is to indicate an ODT setting to the ranks; and
select the target rank to execute the write command.
10. The memory controller of claim 9 , wherein the memory controller device is part of a host processor subsystem.
11. The memory controller of claim 9 , wherein the logic is to send a write command and trigger the target rank to engage ODT in accordance with an ODT value set in a Mode Register.
12. The memory controller of claim 9 , wherein the sequence of the first and second commands is to trigger the target rank to turn on ODT.
13. The memory controller of claim 12 , wherein the logic is to distinguish between the target rank a non-target rank based on the second command.
14. The memory controller of claim 9 , wherein the logic is to select the target rank with a chip select signal, and not select non-target ranks with the chip select signal.
15. An electronic device with a memory subsystem, comprising:
a multi-device package having multiple dynamic random access memory (DRAM) devices organized as a plurality of ranks; and
a memory controller including hardware connectors to couple to the multi-device package, and logic to
send a write command concurrently to multiple ranks of DRAM devices for a write operation, the write command directed to a target rank of DRAM devices to execute the command, including to send multiple sequential commands to generate the write operation;
trigger, without an ODT control pin, target DRAM devices of the target rank to turn on on-die termination (ODT) for the write operation, including sending a first command indicating the write operation and a second command with a column address selection for the write operation, where the sequence of the first and second commands is to indicate an ODT setting to the ranks; and
select the target rank to execute the write command; and
a touchscreen display coupled to generate a display based on data accessed from the DRAM devices.
16. The electronic device of claim 15 , wherein the logic is to send a write command and trigger the target rank to engage ODT in accordance with an ODT value set in a Mode Register.
17. The electronic device of claim 15 , wherein the sequence of the first and second commands is to trigger the target rank to turn on ODT.
18. The electronic device of claim 17 , wherein the logic is to distinguish between the target rank a non-target rank based on the second command.
19. The electronic device of claim 15 , wherein the logic is to select the target rank with an enable signal, and not select non-target ranks with the enable signal.